Table 100. Ecc Result Relevant Bits - ST STM32F102 Series Reference Manual

RM0008
ECC result registers 2/3 (FSMC_ECCR2/3)
Address offset: 0xA000 0000 + 0x54 + 0x20 * (x – 1), x = 2 or 3
Reset value: 0x0000 0000
These registers contain the current error correction code value computed by the ECC
computation modules of the FSMC controller (one module per NAND Flash memory bank).
When the CPU reads the data from a NAND Flash memory page at the correct address
(refer to Section 18.6.5: Error correction code computation ECC (NAND
read from or written to the NAND Flash are processed automatically by ECC computation
module. At the end of X bytes read (according to the ECCPS field in the FSMC_PCRx
registers), the CPU must read the computed ECC value from the FSMC_ECCx registers,
and then verify whether these computed parity data are the same as the parity value
recorded in the spare area, to determine whether a page is valid, and, to correct it if
applicable. The FSMC_ECCRx registers should be cleared after being read by setting the
ECCEN bit to zero. For computing a new data block, the ECCEN bit must be set to one.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:0 ECCx: ECC result.
This field provides the value computed by the ECC computation logic.
describes the contents of these bit fields.

Table 100. ECC result relevant bits

ECCPS[2:0]
000
001
010
011
100
101
Flexible static memory controller (FSMC)
ECCx
r
Page size in bytes
256
512
1024
2048
4096
8192
Flash)), the data
9 8 7 6 5 4 3
Table 100 hereafter
ECC bits
ECC[21:0]
ECC[23:0]
ECC[25:0]
ECC[27:0]
ECC[29:0]
ECC[31:0]
2 1 0
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