Can Filter Registers - ST STM32F102 Series Reference Manual

Controller area network (bxCAN)
Bits 23:16 DATA6[7:0]: Data Byte 6
Data byte 2 of the message.
Bits 15:8 DATA5[7:0]: Data Byte 5
Data byte 1 of the message.
Bits 7:0 DATA4[7:0]: Data Byte 4
Data byte 0 of the message.
21.6.4

CAN filter registers

CAN filter master register (CAN_FMR)
Address offset: 0x200
Reset value: 0x2A1C 0E01
Note: All bits of this register are set and cleared by software.
31 30 29
15 14 13
Bits 31:1 Reserved, forced to reset value
Bit 0 FINIT: Filter Init Mode
Initialization mode for filter banks
0: Active filters mode.
1: Initialization mode for the filters.
CAN filter mode register (CAN_FM1R)
Address offset: 0x204
Reset value: 0x00
Note: This register can be written only when the filter initialization mode is set (FINIT=1) in the
CAN_FMR register.
31 30 29
15 14 13
Reserved FBM13 FBM12 FBM11 FBM10
Res. rw
Note: Please refer to
page 510
534/690
28 27 26 25
12 11 10 9
28 27 26 25
12 11 10 9
FBM9
rw rw rw rw
Figure 199: Filter bank scale configuration - register organization on
24 23 22
Reserved
8 7 6
Reserved
Res.
24 23 22
Reserved
8 7 6
FBM8 FBM7 FBM6 FBM5
rw rw rw
21 20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
FBM4 FBM3 FBM2
rw rw rw rw
RM0008
17 16
1 0
FINIT
rw
17 16
1 0
FBM1 FBM0
rw rw