Sdio Data Counter Register (Sdio_Dcount) - ST STM32F102 Series Reference Manual

RM0008
Bit 2 DTMODE: Data transfer mode selection
0: Block data transfer.
1: Stream data transfer.
Bit 1 DTDIR: Data transfer direction selection
0: From controller to card.
1: From card to controller.
[0] DTEN: Data transfer enabled bit.
Data transfer starts if 1b is written to the DTEN bit. Depending on the direction bit, DTDIR, the
DPSM moves to the Wait_S, Wait_R state or Readwait if RW Start is set immediately at the
beginning of the transfer. It is not necessary to clear the enable bit after the end of a data transfer
but the SDIO_DCTRL must be updated to enable a new data transfer
Note: After a data write, data cannot be written to this register for seven HCLK clock periods.
19.9.10

SDIO Data Counter Register (SDIO_DCOUNT)

Address offset: 0x30
Reset value: 0x0000 0000
The SDIO_DCOUNT register loads the value from the data length register (see
SDIO_DLEN) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As
data is transferred, the counter decrements the value until it reaches 0. The DPSM then
moves to the Idle state and the data status end flag, DATAEND, is set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Res.
Bits 31:25 Reserved, always read as 0.
Bits 24:0 DATACOUNT: Data count value.
When this bit is read, the number of remaining data bytes to be transferred is returned. Write has no
effect.
Note: This register should be read only when the data transfer is complete.
9 8 7
DATACOUNT
r
SDIO interface (SDIO)
6 5 4 3 2 1 0
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