Power Reset; Backup Domain Reset; Clocks; Figure 7. Reset Circuit - ST STM32F102 Series Reference Manual

Reset and clock control (RCC)
For further information on the User Option Bytes, refer to the STM32F10xxx Flash
programming manual.
6.1.2

Power reset

A power reset is generated when one of the following events occurs:
1. Power-on/power-down reset (POR/PDR reset)
2. When exiting Standby mode
A power reset sets all registers to their reset values except the Backup domain (see
Figure 4)
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address
details, refer to
Figure 7.
External
Reset
The Backup domain has two specific resets that affect only the Backup domain (see
Figure 4).
6.1.3

Backup domain reset

A backup domain reset is generated when one of the following events occurs:
1. Software reset, triggered by setting the BDRST bit in the
register
2. V
DD
6.2

Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):
●
HSI oscillator clock
●
HSE oscillator clock
●
PLL clock
The devices have the following two secondary clock sources:
●
40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop/Standby mode.
●
32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK)
70/690
Table 36: Vector table on page
Reset circuit
V
DD
NRST
(RCC_BDCR).
or V power on, if both supplies have previously been powered off.
BAT
0x0000_0004
123.
/V
DDA
R
PU
Filter
Pulse
generator
(min 20 µs)
in the memory map. For more
System Reset
WWDG Reset
IWDG Reset
Power Reset
Software Reset
Low-power management Reset
Backup domain control
RM0008