ST STM32F102 Series Reference Manual page 587

RM0008
Slave address transmission
Then the slave address is sent to the SDA line via the internal shift register.
●
In 10-bit addressing mode, sending the header sequence causes the following event:
–
Then the master waits for a read of the SR1 register followed by a write in the DR
register with the second address byte (see
sequencing).
–
Then the master waits for a read of the SR1 register followed by a read of the SR2
register (see
● In 7-bit addressing mode, one address byte is sent.
As soon as the address byte is sent,
–
Then the master waits for a read of the SR1 register followed by a read of the SR2
register (see
The master can decide to enter Transmitter or Receiver mode depending on the LSB of the
slave address sent.
●
In 7-bit addressing mode,
–
–
●
In 10-bit addressing mode,
–
–
The TRA bit indicates whether the master is in Receiver or Transmitter mode.
Master transmitter
Following the address transmission and after clearing ADDR, the master sends bytes from
the DR register to the SDA line via the internal shift register.
The master waits until TxE is cleared, (see
When the acknowledge pulse is received:
●
The TxE bit is set by hardware and an interrupt is generated if the ITEVFEN and
ITBUFEN bits are set.
If TxE is set and a data byte was not written in the DR register before the end of the last data
transmission, BTF is set and the interface waits until BTF is cleared.
The ADD10 bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
Figure 234 &
The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
Figure 234 &
To enter Transmitter mode, a master sends the slave address with LSB reset.
To enter Receiver mode, a master sends the slave address with LSB set.
To enter Transmitter mode, a master sends the header (11110xx0) and then the
slave address with LSB reset, (where xx denotes the two most significant bits of
the address).
To enter Receiver mode, a master sends the header (11110xx0) and then the
slave address with LSB reset. Then it should send a repeated Start condition
followed by the header (11110xx1), (where xx denotes the two most significant bits
of the address).
Inter-integrated circuit (I
Figure 234
Figure 235 Transfer sequencing).
Figure 235 Transfer sequencing).
Figure 234
& Figure 235 Transfer
Transfer sequencing EV8).
2
C) interface
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