Table 18. Debug Interface Signals; Table 19. Debug Port Mapping - ST STM32F102 Series Reference Manual

RM0008
Table 18.
To optimize the number of free GPIOs during debugging, this mapping can be configured in
different ways by programming the SWJ_CFG[1:0] bits in the
configuration register
Table 19.
SWJ
_CFG
[2:0]
000
001
010
100
Other Forbidden
1. Released only if not using asynchronous trace.
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Debug interface signals
Alternate function
JTMS / SWDIO
JTCK / SWCLK
JTDI
JTDO / TRACESWO
JNTRST
TRACECK
TRACED0
TRACED1
TRACED2
TRACED3
(AFIO_MAPR). Refer to
Debug port mapping
Available debug ports
Full SWJ (JTAG-DP + SW-DP)
(Reset state)
Full SWJ (JTAG-DP + SW-DP)
but without JNTRST
JTAG-DP Disabled and
SW-DP Enabled
JTAG-DP Disabled and
SW-DP Disabled
GPIO port
PA13
PA14
PA15
PB3
PB4
PE2
PE3
PE4
PE5
PE6
AF remap and debug I/O
Table 19
SWJ I/O pin assigned
PA.13 / PA.14 /
PA.15 /
JTMS/ JTCK/S
JTDI
SWDIO WCLK
X X
X X
X X
free free
PB.3 /
JTDO/ PB.4/
TRACE JNTRST
SWO
X X
X x
(1)
free free
free free
111/690
X
free
free
free