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RM0041
Reference manual
STM32F100xx
®
advanced Arm
-based 32-bit MCUs
Introduction
This document is addressed to application developers. It provides complete information on
how to use the STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB,
STM32F100xC, STM32F100xD, and STM32F100xE microcontroller memory and
peripherals.
These devices (STM32F100 Value Line) are a family of microcontrollers with different
memory sizes, packages and peripherals, and are referred to as STM32F100xx throughout
the document, unless otherwise specified.
For ordering information, mechanical and electrical device characteristics, refer to the
datasheets. For information on programming, erasing and protection of the internal flash
memory, refer to PM0063 "STM32F100xx value line Flash programming".
®
®
®
For information on the Arm
Cortex
-M3 core, refer to the Cortex
-M3 Technical Reference
Manual.
Related documents
Available from www.arm.com:
®
• Cortex
-M3 Technical Reference Manual
Available from www.st.com:
• STM32F100xx datasheets
• STM32F100xx flash programming manual
December 2022
RM0041 Rev 6
1/709
www.st.com
1
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Table of Contents
Related Manuals for ST STM32F100 Series
Summary of Contents for ST STM32F100 Series
- Page 1 -M3 core, refer to the Cortex -M3 Technical Reference Manual. Related documents Available from www.arm.com: ® • Cortex -M3 Technical Reference Manual Available from www.st.com: • STM32F100xx datasheets • STM32F100xx flash programming manual December 2022 RM0041 Rev 6 1/709 www.st.com...
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Page 2: Table Of Contents
Contents RM0041 Contents Documentation conventions ....... . . 32 List of abbreviations for registers ....... 32 Glossary . - Page 3 RM0041 Contents Low-power modes ......... . 55 4.3.1 Slowing down system clocks .
- Page 4 Contents RM0041 6.2.6 System clock (SYSCLK) selection ......78 6.2.7 Clock security system (CSS) ....... . . 78 6.2.8 RTC clock .
- Page 5 RM0041 Contents 7.2.4 Port output data register (GPIOx_ODR) (x=A..G) ....115 7.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) ....115 7.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) .
- Page 6 Contents RM0041 8.3.3 Rising trigger selection register (EXTI_RTSR) ....141 8.3.4 Falling trigger selection register (EXTI_FTSR) ....141 8.3.5 Software interrupt event register (EXTI_SWIER) .
- Page 7 RM0041 Contents 10.3.5 Continuous conversion mode ....... 165 10.3.6 Timing diagram ......... . 165 10.3.7 Analog watchdog .
- Page 8 Contents RM0041 11.3.3 DAC data format ......... 192 11.3.4 DAC conversion .
- Page 9 RM0041 Contents 11.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) ......... 209 11.5.12 DAC channel1 data output register (DAC_DOR1) .
- Page 10 Contents RM0041 12.4.5 TIM1 status register (TIMx_SR) ......265 12.4.6 TIM1 event generation register (TIMx_EGR) ....266 12.4.7 TIM1 capture/compare mode register 1 (TIMx_CCMR1) .
- Page 11 RM0041 Contents 13.3.16 Debug mode ..........320 13.4 TIMx2 to TIM5 registers .
- Page 12 Contents RM0041 14.3.10 One-pulse mode ......... 358 14.3.11 TIM12 external trigger synchronization .
- Page 13 RM0041 Contents 15.4 TIM15/16/17 functional description ......393 15.4.1 Time-base unit ......... . . 393 15.4.2 Counter modes .
- Page 14 Contents RM0041 15.6.1 TIM16&TIM17 control register 1 (TIMx_CR1) ....437 15.6.2 TIM16&TIM17 control register 2 (TIMx_CR2) ....438 15.6.3 TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER) .
- Page 15 RM0041 Contents 17.1 RTC introduction ......... . 469 17.2 RTC main features .
- Page 16 Contents RM0041 19.5 Debug mode ..........490 19.6 WWDG registers .
- Page 17 RM0041 Contents 21.3.9 SPI communication using DMA (direct memory addressing) ..555 21.3.10 Error flags ..........557 21.3.11 SPI interrupts .
- Page 18 Contents RM0041 22.6.9 C TRISE register (I2C_TRISE) ......596 22.6.10 I2C register map ......... 598 Universal synchronous asynchronous receiver transmitter (USART) .
- Page 19 RM0041 Contents 24.2 HDMI-CEC main features ........648 24.3 HDMI-CEC bus topology .
- Page 20 Contents RM0041 25.3.1 Mechanism to select the JTAG-DP or the SW-DP ....672 25.4 Pinout and debug port pins ........672 25.4.1 SWJ debug port pins .
- Page 21 RM0041 Contents 25.16.3 TPUI formatter ......... . . 694 25.16.4 TPUI frame synchronization packets .
- Page 22 List of tables RM0041 List of tables Table 1. Low and medium-density device register boundary addresses ..... 37 Table 2. High-density device register boundary addresses .
- Page 23 RM0041 List of tables Table 49. AFIO register map and reset values ......... 130 Table 50.
- Page 24 List of tables RM0041 Table 100. FSMC_BCRx bit fields ........... 506 Table 101.
- Page 25 RM0041 List of tables Table 148. 32-bit debug port registers addressed through the shifted value A[3:2] ... . . 679 Table 149. Packet request (8-bits) ........... 680 Table 150.
- Page 26 List of figures RM0041 List of figures Figure 1. Low and medium density value line system architecture ......34 Figure 2.
- Page 27 RM0041 List of figures Figure 47. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) ..219 Figure 48. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) ..219 Figure 49.
- Page 28 List of figures RM0041 Figure 99. Counter timing diagram, internal clock divided by 4 ......292 Figure 100.
- Page 29 RM0041 List of figures Figure 151. Output compare mode, toggle on OC1........357 Figure 152.
- Page 30 List of figures RM0041 Figure 199. Independent watchdog block diagram ........482 Figure 200.
- Page 31 RM0041 List of figures Figure 245. Configurable stop bits ........... . 605 Figure 246.
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Page 32: Documentation Conventions
Documentation conventions RM0041 Documentation conventions List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value. -
Page 33: General Information
RM0041 Documentation conventions General information ® ® The STM32F100xx MCUs are based on an Arm Cortex core. Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. RM0041 Rev 6 33/709... -
Page 34: Memory And Bus Architecture
Memory and bus architecture RM0041 Memory and bus architecture System architecture In low-and medium-density value line devices, the main system consists of: • Three masters: ® – Cortex -M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 (general-purpose DMA) •... -
Page 35: Figure 2. High Density Value Line System Architecture
RM0041 Memory and bus architecture In high-density value line devices, the main system consists of: • Four masters: ® – Cortex -M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) • Four slaves: – Internal SRAM –... -
Page 36: Memory Organization
Memory and bus architecture RM0041 System bus ® This bus connects the system bus of the Cortex -M3 core (peripherals bus) to a bus matrix which manages the arbitration between the core and the DMA. DMA bus This bus connects the AHB master interface of the DMA to the bus matrix which manages the access of CPU DCode and DMA to the SRAM, flash memory and peripherals. -
Page 37: Memory Map
RM0041 Memory and bus architecture Memory map See the datasheet corresponding to the used device for a comprehensive diagram of the memory map. Table 1 Table 2 give the boundary addresses of the peripherals available in all STM32F100xx devices. Table 1. Low and medium-density device register boundary addresses Boundary address Peripheral Register map... -
Page 38: Table 2. High-Density Device Register Boundary Addresses
Memory and bus architecture RM0041 Table 1. Low and medium-density device register boundary addresses (continued) Boundary address Peripheral Register map 0x4000 7C00 - 0x4000 FFFF Reserved 0x4000 7800 - 0x4000 7BFF Section 24.9.8 on page 668 0x4000 7400 - 0x4000 77FF Section 11.5.15 on page 210 0x4000 7000 - 0x4000 73FF Power control PWR... - Page 39 RM0041 Memory and bus architecture Table 2. High-density device register boundary addresses (continued) Boundary address Peripheral Register map 0x4001 4C00 - 0x4001 FFFF Reserved 0x4001 4800 - 0x4001 4BFF TIM17 timer Section 15.6.16 on page 454 0x4001 4400 - 0x4001 47FF TIM16 timer Section 15.6.16 on page 454 0x4001 4000 - 0x4001 43FF...
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Page 40: Embedded Sram
Memory and bus architecture RM0041 Table 2. High-density device register boundary addresses (continued) Boundary address Peripheral Register map 0x4000 7C00 - 0x4000 FFFF Reserved 0x4000 7800 - 0x4000 7BFF Section 24.9.8 on page 668 0x4000 7400 - 0x4000 77FF Section 11.5.15 on page 210 0x4000 7000 - 0x4000 73FF Power control PWR Section 4.4.3 on page 63... -
Page 41: Bit Banding
RM0041 Memory and bus architecture 2.3.2 Bit banding ® The Cortex -M3 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region. -
Page 42: Table 3. Flash Module Organization (Low-Density Value Line Devices)
Memory and bus architecture RM0041 The flash memory interface (FLASH) features: • Read interface (32-bit) • Option byte loader • Flash Program/Erase operation • Read/write protection Table 3. Flash module organization (low-density value line devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte... -
Page 43: Table 4. Flash Module Organization (Medium-Density Value Line Devices)
RM0041 Memory and bus architecture Table 4. Flash module organization (medium-density value line devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte Page 3... -
Page 44: Table 5. Flash Module Organization (High-Density Value Line Devices)
Memory and bus architecture RM0041 Table 5. Flash module organization (high-density value line devices) (continued) Block Name Base addresses Size (bytes) FLASH_ACR 0x4002 2000 - 0x4002 2003 FLASH_KEYR 0x4002 2004 - 0x4002 2007 FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B FLASH_SR 0x4002 200C - 0x4002 200F Flash memory interface... -
Page 45: Boot Configuration
RM0041 Memory and bus architecture For complete information on flash memory operations and register configurations, refer to PM00063). Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved HLFCYA Reserved Reserved Bits 31:4 Reserved, must be kept cleared. Bit 3 HLFCYA: Flash half cycle access enable 0: Half cycle is disabled 1: Half cycle is enabled... - Page 46 Embedded boot loader The embedded boot loader is used to reprogram the flash memory using the USART1 serial interface. This program is located in the system memory and is programmed by ST during production. For further details refer to AN2606.
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Page 47: Crc Calculation Unit
RM0041 CRC calculation unit CRC calculation unit Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 48: Crc Functional Description
CRC calculation unit RM0041 CRC functional description The CRC calculation unit mainly consists of a single 32-bit data register, which: • is used as an input register to enter new data in the CRC calculator (when writing into the register) •... -
Page 49: Control Register (Crc_Cr)
RM0041 CRC calculation unit Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 General-purpose 8-bit data register bits Can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register. -
Page 50: Power Control (Pwr)
Power control (PWR) RM0041 Power control (PWR) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 51: Independent A/D And D/A Converter Supply And Reference Voltage
RM0041 Power control (PWR) 4.1.1 Independent A/D and D/A converter supply and reference voltage To improve conversion accuracy, the ADC and the DAC have an independent power supply that can be separately filtered and shielded from noise on the PCB. •... -
Page 52: Voltage Regulator
Power control (PWR) RM0041 When the backup domain is supplied by V (analog switch connected to V ), the following functions are available: • PC14 and PC15 can be used as either GPIO or LSE pins • PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or second output (refer to Section 5: Backup registers (BKP)) -
Page 53: Programmable Voltage Detector (Pvd)
RM0041 Power control (PWR) Figure 5. Power on reset/power down reset waveform VDD/VDDA VPOR/PDR rising edge 40 mV VPOR/PDR hysteresis falling edge Temporization tRSTTEMPO Reset MS30431V2 4.2.2 Programmable voltage detector (PVD) The PVD can be used to monitor the V power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register... -
Page 54: Figure 6. Pvd Thresholds
Power control (PWR) RM0041 Figure 6. PVD thresholds VPVD rising edge 100 mV PVD threshold VPVD hysteresis falling edge PVD output MS30432V3 54/709 RM0041 Rev 6... -
Page 55: Low-Power Modes
RM0041 Power control (PWR) Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several low- power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. -
Page 56: Peripheral Clock Gating
Power control (PWR) RM0041 4.3.2 Peripheral clock gating In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. -
Page 57: Stop Mode
RM0041 Power control (PWR) Table 9. Sleep-now Sleep-now mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 and Mode entry – SLEEPONEXIT = 0 ® Refer to the Cortex -M3 System Control register. If WFI was used for entry: Interrupt: Refer to Table 50: Vector table for STM32F100xx devices... -
Page 58: Table 11. Stop Mode
Power control (PWR) RM0041 In Stop mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 18.3: IWDG functional description. -
Page 59: Standby Mode
RM0041 Power control (PWR) 4.3.5 Standby mode The Standby mode allows to achieve the lowest power consumption. It is based on the ® Cortex -M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also switched off. -
Page 60: Auto-Wakeup (Awu) From Low-Power Mode
Power control (PWR) RM0041 I/O states in Standby mode In Standby mode, all I/O pins are high impedance except: • Reset pad (still available) • TAMPER pin if configured for tamper or calibration out • WKUP pin, if enabled Debug mode By default, the debug connection is lost if the application puts the MCU in Stop or Standby ®... - Page 61 RM0041 Power control (PWR) Bits 31:9 Reserved, must be kept at reset value.. Bit 8 DBP: Disable backup domain write protection. In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and Backup registers disabled 1: Access to RTC and Backup registers enabled Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1.
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Page 62: Power Control/Status Register (Pwr_Csr)
Power control (PWR) RM0041 4.4.2 Power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. Reserved EWUP PVDO Reserved Reserved Bits 31:9 Reserved, must be kept at reset value. -
Page 63: Pwr Register Map
RM0041 Power control (PWR) 4.4.3 PWR register map The following table summarizes the PWR registers. Table 13. PWR register map and reset values Offset Register PWR_CR [2:0] 0x000 Reserved Reset value 0 0 0 0 0 0 0 0 0 PWR_CSR 0x004 Reserved... -
Page 64: Backup Registers (Bkp)
Backup registers (BKP) RM0041 Backup registers (BKP) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 65: Bkp Functional Description
RM0041 Backup registers (BKP) BKP functional description 5.3.1 Tamper detection The TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR). -
Page 66: Bkp Registers
Backup registers (BKP) RM0041 BKP registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 5.4.1 Backup data register x (BKP_DRx) (x = 1 ..20) Address offset: 0x04 to 0x28, 0x40 to 0x64 Reset value: 0x0000 0000 D[15:0]... -
Page 67: Backup Control Register (Bkp_Cr)
RM0041 Backup registers (BKP) Bit 8 ASOE: Alarm or second output enable Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit. The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled while the ASOE bit is set. - Page 68 Backup registers (BKP) RM0041 Bits 15:10 Reserved, must be kept at reset value. Bit 9 TIF: Tamper interrupt flag This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is cleared by writing 1 to the CTI bit (also clears the interrupt). It is also cleared if the TPIE bit is reset.
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Page 69: Bkp Register Map
RM0041 Backup registers (BKP) 5.4.5 BKP register map BKP registers are mapped as 16-bit addressable registers as described in the table below: Table 14. BKP register map and reset values Offset Register 0x00 Reserved BKP_DR1 D[15:0] 0x04 Reserved Reset value BKP_DR2 D[15:0] 0x08... - Page 70 Backup registers (BKP) RM0041 Table 14. BKP register map and reset values (continued) Offset Register 0x38 to Reserved 0x3C BKP_DR11 D[15:0] 0x40 Reserved Reset value BKP_DR12 D[15:0] 0x44 Reserved Reset value BKP_DR13 D[15:0] 0x48 Reserved Reset value BKP_DR14 D[15:0] 0x4C Reserved Reset value BKP_DR15...
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Page 71: Reset And Clock Control (Rcc)
RM0041 Reset and clock control (RCC) Reset and clock control (RCC) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 72: Power Reset
Reset and clock control (RCC) RM0041 6.1.2 Power reset A power reset is generated when one of the following events occurs: Power-on/power-down reset (POR/PDR reset) When exiting Standby mode A power reset sets all registers to their reset values except the Backup domain (see Figure These sources act on the NRST pin and it is always kept low during the delay phase. -
Page 73: Figure 8. Stm32F100Xx Clock Tree (Low And Medium-Density Devices)
RM0041 Reset and clock control (RCC) The devices have the following two secondary clock sources: • 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode. • 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real- time clock (RTCCLK) Each clock source can be switched on or off independently when it is not used, to optimize... -
Page 74: Figure 9. Stm32F100Xx Clock Tree (High-Density Devices)
Reset and clock control (RCC) RM0041 Figure 9. STM32F100xx clock tree (high-density devices) FLITFCLK to Flash programming interface 8 MHz HSI RC FSMCLK to FSMC Peripheral clock Enable HCLK 24 MHz max to AHB bus, core, memory and DMA Clock Enable to Cortex System timer PLLSRC... -
Page 75: Hse Clock
RM0041 Reset and clock control (RCC) Manual.http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/DDI0337E_cortex_m3_r1p1 _trm.pdf 6.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: • HSE external crystal/ceramic resonator • HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. -
Page 76: Hsi Clock
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T =25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the... -
Page 77: Lse Clock
RM0041 Reset and clock control (RCC) An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt register (RCC_CIR). 6.2.4 LSE clock The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions. -
Page 78: System Clock (Sysclk) Selection
Reset and clock control (RCC) RM0041 Enable TIM5 timer and configure channel4 in input capture mode Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purposes. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or interrupt. -
Page 79: Watchdog Clock
RM0041 Reset and clock control (RCC) The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: • If LSE is selected as RTC clock: – The RTC continues to work even if the V supply is switched off, provided the supply is maintained. -
Page 80: Rcc Registers
Reset and clock control (RCC) RM0041 RCC registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. 6.3.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access PLLON Reserved... - Page 81 RM0041 Reset and clock control (RCC) Bit 16 HSEON: External high-speed clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering in Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration...
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Page 82: Clock Configuration Register (Rcc_Cfgr)
Reset and clock control (RCC) RM0041 6.3.2 Clock configuration register (RCC_CFGR) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. MCO[2:0] PLLMUL[3:0] XTPRE... - Page 83 RM0041 Reset and clock control (RCC) Bit 17 PLLXTPRE: LSB of division factor PREDIV1 Set and cleared by software to select the least significant bit of the PREDIV1 division factor. It is the same bit as bit 0 in the RCC_CFGR2 register, so modifying bit 0 in the RCC_CFGR2 register changes this bit accordingly.
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Page 84: Clock Interrupt Register (Rcc_Cir)
Reset and clock control (RCC) RM0041 Bits 3:2 SWS: System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 00: HSI oscillator used as system clock 01: HSE oscillator used as system clock 10: PLL used as system clock 11: not applicable Bits 1:0 SW: System clock switch... - Page 85 RM0041 Reset and clock control (RCC) Bit 18 HSIRDYC: HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag. 0: No effect 1: HSIRDYF cleared Bit 17 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: LSERDYF cleared Bit 16 LSIRDYC: LSI ready interrupt clear...
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Page 86: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Reset and clock control (RCC) RM0041 Bit 4 PLLRDYF: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. Cleared by software setting the PLLRDYC bit. 0: No clock ready interrupt caused by PLL lock 1: Clock ready interrupt caused by PLL lock Bit3 HSERDYF: HSE ready interrupt flag Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set. - Page 87 RM0041 Reset and clock control (RCC) Bit 18 TIM17RST: TIM17 reset Set and cleared by software. 0: No effect 1: Reset TIM17 Bit 17 TIM16RST: TIM16 reset Set and cleared by software. 0: No effect 1: Resets TIM16 Bit 16 TIM15RST: TIM15 reset Set and cleared by software.
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Page 88: Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)
Reset and clock control (RCC) RM0041 Bit 5 IOPDRST: IO port D reset Set and cleared by software. 0: No effect 1: Reset I/O port D Bit 4 IOPCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset I/O port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. - Page 89 RM0041 Reset and clock control (RCC) Bit 28 PWRRST: Power interface reset Set and cleared by software. 0: No effect 1: Reset power interface Bit 27 BKPRST: Backup interface reset Set and cleared by software. 0: No effect 1: Reset backup interface Bits 26:23 Reserved, always read as 0.
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Page 90: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
Reset and clock control (RCC) RM0041 Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: No effect 1: Reset window watchdog Bits 10:9 Reserved, always read as 0. Bit 8 TIM14RST: Timer 14 reset Set and cleared by software. 0: No effect 1: Reset timer 14 Bit 7 TIM13RST: Timer 13 reset... - Page 91 RM0041 Reset and clock control (RCC) Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. Reserved FLITF SRAM...
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Page 92: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
Reset and clock control (RCC) RM0041 6.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x18 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going. - Page 93 RM0041 Reset and clock control (RCC) Bit 11 TIM1EN: TIM1 Timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1 timer clock enabled Bit 10 Reserved. Bit 9 ADC1EN: ADC 1 interface clock enable Set and cleared by software. 0: ADC 1 interface disabled 1: ADC 1 interface clock enabled Bit 8 IOPGEN: I/O port G clock enable...
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Page 94: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
Reset and clock control (RCC) RM0041 6.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. - Page 95 RM0041 Reset and clock control (RCC) Bit 21 I2C1EN: I2C 1 clock enable Set and cleared by software. 0: I2C 1 clock disabled 1: I2C 1 clock enabled Bit 20 UART5EN: UART 5 clock enable Set and cleared by software. 0: UART 5 clock disabled 1: UART 5 clock enabled Bit 19 UART4EN: UART 4 clock enable...
- Page 96 Reset and clock control (RCC) RM0041 Bit 6 TIM12EN: Timer 12 clock enable Set and cleared by software. 0: Timer 12 clock disabled 1: Timer 12 clock enabled Bit 5 TIM7EN: Timer 7clock enable Set and cleared by software. 0: Timer 7 clock disabled 1: Timer 7 clock enabled Bit 4 TIM6EN: Timer 6 clock enable Set and cleared by software.
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Page 97: Backup Domain Control Register (Rcc_Bdcr)
RM0041 Reset and clock control (RCC) 6.3.9 Backup domain control register (RCC_BDCR) Address offset: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register... -
Page 98: Control/Status Register (Rcc_Csr)
Reset and clock control (RCC) RM0041 Bit 1 LSERDY: External low-speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. - Page 99 RM0041 Reset and clock control (RCC) Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs.
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Page 100: Clock Configuration Register2 (Rcc_Cfgr2)
Reset and clock control (RCC) RM0041 6.3.11 Clock configuration register2 (RCC_CFGR2) Address offset: 0x2C Access: no wait state, word, half-word and byte access Reset value: 0x0000 0000 Reserved PREDIV1[3:0] Reserved Bits 31:4 Reserved. Bits 3:0 PREDIV1[3:0]: PREDIV1 division factor Set and cleared by software to select the PREDIV1 division factor. These bits can be written only when the PLL is disabled. -
Page 101: Rcc Register Map
RM0041 Reset and clock control (RCC) 6.3.12 RCC register map The following table gives the RCC register map and the reset values. Table 15. RCC register map and reset values Offset Register RCC_CR HSICAL[7:0] HSITRIM[4:0] 0x000 Reserved Reserved Reset value PPRE2 PPRE1 RCC_CFGR... -
Page 102: General-Purpose And Alternate-Function I/Os
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. -
Page 103: Figure 11. Basic Structure Of A Standard I/O Port Bit
RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 11. Basic structure of a standard I/O port bit Analog Input To on-chip peripheral on/off Alternate Function Input on/off Read TTL Schmitt Protection trigger on/off diode Input driver I/O pin Write Output driver Protection diode... -
Page 104: General-Purpose I/O (Gpio)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 Table 16. Port bit configuration table PxODR Configuration mode CNF1 CNF0 MODE1 MODE0 register Push-pull 0 or 1 General purpose output Open-drain 0 or 1 Push-pull Don’t care Alternate Function Table 17 output Open-drain Don’t care... -
Page 105: External Interrupt/Wakeup Lines
RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) for reset only GPIOx_BRR) to select the bits to modify. The unselected bits will not be modified. 7.1.3 External interrupt/wakeup lines All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode. -
Page 106: Input Configuration
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 7.1.7 Input configuration When the I/O Port is programmed as Input: • The Output Buffer is disabled • The Schmitt Trigger Input is activated • The weak pull-up and pull-down resistors are activated or not depending on input configuration (pull-up, pull-down or floating): •... -
Page 107: Alternate Function Configuration
RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 14. Output configuration Read or V DD_FT TTL Schmitt Protection trigger diode Write Input driver I/O pin Output driver Protection diode P-MOS Output control Read/write N-MOS Push-pull or Open-drain ai14784 1. V is a potential specific to 5-Volt tolerant I/Os, and different from V DD_FT 7.1.9... -
Page 108: Analog Configuration
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 Figure 15. Alternate function configuration Alternate Function Input To on-chip peripheral Read or V DD_FT TTL Schmitt Protection trigger diode Input driver I/O pin Write Output driver Protection diode P-MOS Output control N-MOS Read/write push-pull or... -
Page 109: Gpio Configurations For Device Peripherals
RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 16. High impedance-analog configuration Analog Input To on-chip peripheral Read or V DD_FT TTL Schmitt Protection trigger diode Write Input driver I/O pin Protection diode Read/write From on-chip peripheral ai14786 7.1.11 GPIO configurations for device peripherals Table 18 Table 27... -
Page 110: Table 21. General-Purpose Timers Tim12/13/14
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 Table 20. General-purpose timers TIM15/16/17 TIM15/16/17 pinout Configuration GPIO configuration TIM15/16/17_BKIN Break input Input floating TIM15/16/17_ETR External trigger timer input Input floating Table 21. General-purpose timers TIM12/13/14 TIM12/13/14 pinout Configuration GPIO configuration Input capture channel x Input floating TIM12/13/14_CHx... -
Page 111: Table 24. Cec
RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 23. SPI (continued) SPI pinout Configuration GPIO configuration Hardware master /slave Input floating/ Input pull-up / Input pull-down SPIx_NSS Hardware master/ NSS output enabled Alternate function push-pull Software Not used. Can be used as a GPIO Table 24. -
Page 112: Table 27. Other Ios
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 Table 27. Other IOs Pins Alternate function GPIO configuration RTC output Forced by hardware when configuring the TAMPER-RTC pin BKP_CR and BKP_RTCCR registers Tamper event input Clock output Alternate function push-pull EXTI input lines External input interrupts Input floating / input pull-up / input pull-down 112/709... -
Page 113: Gpio Registers
RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) GPIO registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 7.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) Address offset: 0x00 Reset value: 0x4444 4444 CNF7[1:0]... -
Page 114: Port Configuration Register High (Gpiox_Crh) (X=A..g
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 7.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) Address offset: 0x04 Reset value: 0x4444 4444 CNF15[1:0] MODE15[1:0] CNF14[1:0] MODE14[1:0] CNF13[1:0] MODE13[1:0] CNF12[1:0] MODE12[1:0] CNF11[1:0] MODE11[1:0] CNF10[1:0] MODE10[1:0] CNF9[1:0] MODE9[1:0] CNF8[1:0] MODE8[1:0] Bits 31:30, 27:26, CNFy[1:0]: Port x configuration bits (y= 8 .. -
Page 115: Port Output Data Register (Gpiox_Odr) (X=A
RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 7.2.4 Port output data register (GPIOx_ODR) (x=A..G) Address offset: 0x0C Reset value: 0x0000 0000 Reserved ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 Bits 31:16 Reserved, must be kept at reset value. -
Page 116: Port Bit Reset Register (Gpiox_Brr) (X=A..g
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 7.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) Address offset: 0x14 Reset value: 0x0000 0000 Reserved BR15 BR14 BR13 BR12 BR11 BR10 Bits 31:16 Reserved Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only. -
Page 117: Alternate Function I/O And Debug Configuration (Afio)
RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 31:17 Reserved Bit 16 LCKK[16]: Lock key This bit can be read anytime. It can only be modified using the Lock Key Writing Sequence. 0: Port configuration lock key not active 1: Port configuration lock key active. -
Page 118: Jtag/Swd Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 7.3.3 JTAG/SWD alternate function remapping The debug interface signals are mapped on the GPIO ports as shown in Table Table 28. Debug interface signals Alternate function GPIO port JTMS / SWDIO PA13 JTCK / SWCLK PA14 JTDI... -
Page 119: Table 30. Tim5 Alternate Function Remapping
RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 30. TIM5 alternate function remapping Alternate function TIM5CH4_IREMAP = 0 TIM5CH4_IREMAP = 1 TIM5 Channel 4 is LSI internal clock is connected to TIM5_CH4 TIM5_CH4 connected to PA3 input for calibration purpose. 1. -
Page 120: Table 36. Tim2 Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 1. Remap available only for 64-pin, 100-pin and 144-pin packages. Table 36. TIM2 alternate function remapping TIM2_REMAP TIM2_REMAP TIM2_REMAP TIM2_REMAP Alternate [1:0] = “00” [1:0] = “01” [1:0] = “10” [1:0] = “11” function (no remap) (partial remap) -
Page 121: Usart Alternate Function Remapping
RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 40. TIM16 remapping Alternate function TIM16_REMAP = 0 TIM16_REMAP = 1 TIM16_CH1 1. Refer to the AF remap and debug I/O configuration register Section 7.4.7: AF remap and debug I/O configuration register (AFIO_MAPR2). -
Page 122: I2C1 Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 7.3.6 I2C1 alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR) Table 45. I2C1 remapping Alternate function I2C1_REMAP = 0 I2C1_REMAP = 1 I2C1_SCL I2C1_SDA 7.3.7 SPI1 alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR) Table 46. -
Page 123: Afio Registers
RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) AFIO registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. Note: To read/write the AFIO_EVCR, AFIO_MAPR, AFIO_MAPR2 and AFIO_EXTICRX registers, the AFIO clock should first be enabled. Refer to APB2 peripheral clock enable register (RCC_APB2ENR). -
Page 124: Af Remap And Debug I/O Configuration Register (Afio_Mapr)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 7.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) Address offset: 0x04 Reset value: 0x0000 0000 TIM5CH4 SWJ_CFG[2:0] _IREMAP Reserved Reserved PD01_ TIM4_ TIM3_REMAP TIM2_REMAP TIM1_REMAP USART3_ USART2_ USART1_ I2C1_ SPI1_ REMAP REMAP [1:0] [1:0]... - Page 125 RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 9:8 TIM2_REMAP[1:0]: TIM2 remapping These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4 and external trigger (ETR) on the GPIO ports. 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) 01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) 10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) 11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
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Page 126: External Interrupt Configuration Register 1 (Afio_Exticr1)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 7.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) Address offset: 0x08 Reset value: 0x0000 Reserved EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 0 to 3) These bits are written by software to select the source input for EXTIx external interrupt. Refer to Section 8.2.5: External interrupt/event line mapping 0000: PA[x] pin... -
Page 127: External Interrupt Configuration Register 3 (Afio_Exticr3)
RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 7.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) Address offset: 0x10 Reset value: 0x0000 Reserved EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 8 to 11) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin... -
Page 128: Af Remap And Debug I/O Configuration Register (Afio_Mapr2)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 7.4.7 AF remap and debug I/O configuration register (AFIO_MAPR2) Address offset: 0x1C Reset value: 0x0000 0000 Reserved MISC TIM67_ TIM12_ DAC_ TIM14_ TIM13_ TIM1_ CEC_ TIM17_ TIM16_ TIM15_ C_NA REMA DMA_ REMA REMA DMA_ REMA... - Page 129 RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bit 8 TIM13_REMAP: TIM13 remapping This bit is set and cleared by software. It controls the mapping of the TIM13_CH1 alternate function onto the GPIO ports. 0: No remap (PC8) 1: Remap (PB0) Bits 7:5 Reserved.
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Page 130: Gpio And Afio Register Maps
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0041 GPIO and AFIO register maps The following tables give the GPIO and AFIO register map and the reset values. Refer to Table 1 on page 37 Table 2 on page 38 for the register boundary addresses. Table 48. - Page 131 RM0041 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 49. AFIO register map and reset values (continued) Offset Register AFIO_EXTICR1 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] 0x08 Reserved Reset value AFIO_EXTICR2 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] 0x0C Reserved Reset value AFIO_EXTICR3 EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] 0x10...
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Page 132: Interrupts And Events
Interrupts and events RM0041 Interrupts and events Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. - Page 133 RM0041 Interrupts and events Table 50. Vector table for STM32F100xx devices (continued) Type of Acronym Description Address priority Non maskable interrupt. The RCC fixed NMI_Handler Clock Security System (CSS) is 0x0000_0008 linked to the NMI vector. fixed HardFault_Handler All class of fault 0x0000_000C MemManage_Handl settable...
- Page 134 Interrupts and events RM0041 Table 50. Vector table for STM32F100xx devices (continued) Type of Acronym Description Address priority settable DMA1_Channel3 DMA1 Channel3 global interrupt 0x0000_0074 settable DMA1_Channel4 DMA1 Channel4 global interrupt 0x0000_0078 settable DMA1_Channel5 DMA1 Channel5 global interrupt 0x0000_007C settable DMA1_Channel6 DMA1 Channel6 global interrupt 0x0000_0080...
- Page 135 RM0041 Interrupts and events Table 50. Vector table for STM32F100xx devices (continued) Type of Acronym Description Address priority settable TIM12 TIM12 global interrupt 0x0000_00EC settable TIM13 TIM13 global interrupt 0x0000_00F0 settable TIM14 TIM14 global interrupt 0x0000_00F4 0x0000_00F8 - Reserved 0x0000_00FC settable FSMC FSMC global interrupt...
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Page 136: External Interrupt/Event Controller (Exti)
Interrupts and events RM0041 External interrupt/event controller (EXTI) The external interrupt/event controller consists of up to 18 edge detectors for generating event/interrupt requests. Each input line can be independently configured to select the type (event or interrupt) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. -
Page 137: Wakeup Event Management
RM0041 Interrupts and events 8.2.3 Wakeup event management The STM32F100xx is able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by: • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling ®... -
Page 138: External Interrupt/Event Line Mapping
Interrupts and events RM0041 Software interrupt/event selection The 18 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt. • Configure the mask bits of the 18 Interrupt/Event lines (EXTI_IMR, EXTI_EMR) • Set the required bit of the software interrupt register (EXTI_SWIER) 8.2.5 External interrupt/event line mapping... -
Page 139: Figure 19. External Interrupt/Event Gpio Mapping
RM0041 Interrupts and events Figure 19. External interrupt/event GPIO mapping EXTI0[3:0] bits in AFIO_EXTICR1 register EXTI0 EXTI1[3:0] bits in AFIO_EXTICR1 register EXTI1 EXTI15[3:0] bits in AFIO_EXTICR4 register PA15 PB15 PC15 EXTI15 PD15 PE15 PF15 PG15 1. To configure the AFIO_EXTICRx for the mapping of external interrupt/event lines onto GPIOs, the AFIO clock should first be enabled. -
Page 140: Exti Registers
Interrupts and events RM0041 registers EXTI Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 8.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 MR17 MR16... -
Page 141: Rising Trigger Selection Register (Exti_Rtsr)
RM0041 Interrupts and events 8.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 TR17 TR16 Reserved TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:18 Reserved, must be kept at reset value (0). Bits 17:0 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Note:... -
Page 142: Software Interrupt Event Register (Exti_Swier)
Interrupts and events RM0041 8.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 SWIER SWIER Reserved SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER Bits 31:18 Reserved, must be kept at reset value (0). Bits 17:0 SWIERx: Software interrupt on line x If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. -
Page 143: Exti Register Map
RM0041 Interrupts and events 8.3.7 EXTI register map The following table gives the EXTI register map and the reset values. Table 51. External interrupt/event controller register map and reset values Offset Register MR[17:0] EXTI_IMR Reserved 0x00 Reset value EMR[17:0] EXTI_EMR Reserved 0x04 Reset value... -
Page 144: Direct Memory Access Controller (Dma)
Direct memory access controller (DMA) RM0041 Direct memory access controller (DMA) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 145: Figure 20. Dma Block Diagram In Low And Medium- Density
RM0041 Direct memory access controller (DMA) Figure 20. DMA block diagram in low and medium- density Cat.1 and Cat.2 STM32F100xx devices ICode FLASH Flash (Flash memory interface) DCode Cortex-M3 SRAM Ch.1 Reset & clock Ch.2 control (RCC) Bridge 2 Ch.7 Bridge 1 APB2 APB1... -
Page 146: Dma Functional Description
Direct memory access controller (DMA) RM0041 Figure 21. DMA block diagram in high-density Cat.4 and Cat.5 STM32F100xx devices ICode Flash FLITF DCode Cortex-M3 Sys tem SRAM DMA1 Ch.1 FSMC Ch.2 Bridge 2 AHB System Ch.7 APB2 Bridge 1 APB1 Arbiter ADC1 DMA request USART1... -
Page 147: Arbiter
RM0041 Direct memory access controller (DMA) DMA controller. Once the request is deasserted by the peripheral, the DMA controller releases the Acknowledge. If there are more requests, the peripheral can initiate the next transaction. In summary, each DMA transfer consists of three operations: •... - Page 148 Direct memory access controller (DMA) RM0041 address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During transfer operations, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in non-circular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero).
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Page 149: Programmable Data Width, Data Alignment And Endians
RM0041 Direct memory access controller (DMA) If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as Circular mode. -
Page 150: Error Management
Direct memory access controller (DMA) RM0041 and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below: • To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord •... -
Page 151: Figure 22. Dma1 Request Mapping
RM0041 Direct memory access controller (DMA) The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral. Figure 22. DMA1 request mapping Fixed hardware priority Peripheral request signals High priority ADC1 HW request 1 Channel 1... -
Page 152: Table 54. Summary Of Dma1 Requests For Each Channel
Direct memory access controller (DMA) RM0041 On low- and medium -density devices the TIM6_DAC1 and TIM7_DAC2 DMA requests are always mapped respectively on DMA1 Channel 3 and DMA1 Channel 4. For more details refer to the AFIO section. Table 54 lists the DMA requests for each channel. -
Page 153: Table 55. Summary Of Dma2 Requests For Each Channel
RM0041 Direct memory access controller (DMA) Figure 23. DMA2 request mapping Peripheral request signals Fixed hardware priority TIM5_CH4 HIGH PRIORITY TIM5_TRIG HW request 1 Channel 1 UART5_TX SPI3_RX SW trigger (MEM2MEM bit) Channel 1 EN bit TIM5_CH3 HW request 2 Channel 2 TIM5_UP SPI3_TX... -
Page 154: Dma Registers
Direct memory access controller (DMA) RM0041 DMA registers Refer to for a list of abbreviations used in register descriptions. Note: In the following registers, all bits related to channel6 and channel7 are not relevant for DMA2 since it has only 5 channels. The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32- bit). -
Page 155: Dma Interrupt Flag Clear Register (Dma
RM0041 Direct memory access controller (DMA) 9.4.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 CTEIF CHTIF CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 Reserved CTEIF CHTIF CTCIF CTEIF CHTIF CGIF4 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 Bits 31:28 Reserved, must be kept at reset value. -
Page 156: Dma Channel X Configuration Register (Dma_Ccrx) (X = 1
Direct memory access controller (DMA) RM0041 9.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number) Address offset: 0x08 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 Reserved MEM2 PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC... -
Page 157: Dma Channel X Number Of Data Register (Dma_Cndtrx) (X = 1
RM0041 Direct memory access controller (DMA) Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 2 HTIE: Half transfer interrupt enable... -
Page 158: Dma Channel X Peripheral Address Register (Dma_Cparx) (X = 1
Direct memory access controller (DMA) RM0041 9.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) Address offset: 0x10 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 PA[31:0]: Peripheral address... -
Page 159: Dma Register Map
RM0041 Direct memory access controller (DMA) 9.4.7 DMA register map The following table gives the DMA register map and the reset values. Table 56. DMA register map and reset values Offset Register DMA_ISR 0x000 Reserved Reset value DMA_IFCR 0x004 Reserved Reset value DMA_CCR1 [1:0]... - Page 160 Direct memory access controller (DMA) RM0041 Table 56. DMA register map and reset values (continued) Offset Register DMA_CCR4 [1:0] 0x044 Reserved Reset value DMA_CNDTR4 NDT[15:0] 0x048 Reserved Reset value DMA_CPAR4 PA[31:0] 0x04C Reset value DMA_CMAR4 MA[31:0] 0x050 Reset value 0x054 Reserved DMA_CCR5 [1:0]...
- Page 161 RM0041 Direct memory access controller (DMA) Table 56. DMA register map and reset values (continued) Offset Register DMA_CMAR7 MA[31:0] 0x08C Reset value 0x090 Reserved Refer to Table 1 on page 37 Table 2 on page 38 for the register boundary addresses. RM0041 Rev 6 161/709...
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Page 162: Analog-To-Digital Converter (Adc)
Analog-to-digital converter (ADC) RM0041 Analog-to-digital converter (ADC) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 163: Adc Functional Description
RM0041 Analog-to-digital converter (ADC) 10.3 ADC functional description Figure 24 shows a single ADC block diagramand Table 57 gives the ADC pin description. Figure 24. Single ADC block diagram Interrupt Flags enable bits End of conversion EOCIE ADC Interrupt to NVIC End of injected conversion JEOC JEOCIE... -
Page 164: Adc On-Off Control
Analog-to-digital converter (ADC) RM0041 Table 57. ADC pins Name Signal type Remarks Input, analog reference The higher/positive reference voltage for the ADC, REF+ ≤ ≤ positive 2.4 V REF+ Analog power supply equal to V Input, analog supply ≤ ≤ 2.4 V 3.6 V Input, analog reference... -
Page 165: Single Conversion Mode
RM0041 Analog-to-digital converter (ADC) Temperature sensor/V internal channels REFINT The temperature sensor is connected to channel ADCx_IN16 and the internal reference voltage V is connected to ADCx_IN17. These two internal channels can be selected REFINT and converted as injected or regular channels. Note: The sensor and V are only available on the master ADC1 peripheral. -
Page 166: Analog Watchdog
Analog-to-digital converter (ADC) RM0041 Figure 25. Timing diagram ADC_CLK ADON SWSTART/ JSWSTART Start 1st conversion Start next conversion ADC conversion Next ADC conversion Conversion time t STAB (total conv. time) Software clears the EOC bit ai16047b 10.3.7 Analog watchdog The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold. -
Page 167: Scan Mode
RM0041 Analog-to-digital converter (ADC) Table 58. Analog watchdog channel selection (continued) ADC_CR1 register control bits (x = don’t care) Channels to be guarded by analog watchdog AWDSGL bit AWDEN bit JAWDEN bit All regular and injected channels Single injected channel Single regular channel Single... -
Page 168: Discontinuous Mode
Analog-to-digital converter (ADC) RM0041 Auto-injection If the JAUTO bit is set, then the injected group channels are automatically converted after the regular group channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADC_SQRx and ADC_JSQR registers. In this mode, external trigger on injected channels must be disabled. -
Page 169: Calibration
RM0041 Analog-to-digital converter (ADC) conversion second trigger: sequence converted 3, 6, 7. An EOC event is generated at each conversion third trigger: sequence converted 9, 10. An EOC event is generated at each conversion fourth trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion Note: When a regular group is converted in discontinuous mode, no rollover will occur. -
Page 170: Data Alignment
Analog-to-digital converter (ADC) RM0041 Figure 28. Calibration timing diagram Calibration Reset by Hardware Calibration ongoing Normal ADC Conversion Conversion 10.5 Data alignment ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion. Data can be left or right aligned as shown in Figure 29. -
Page 171: Channel-By-Channel Programmable Sample Time
RM0041 Analog-to-digital converter (ADC) 10.6 Channel-by-channel programmable sample time ADC samples the input voltage for a number of ADC_CLK cycles which can be modified us- ing the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sample time. The total conversion time is calculated as follows: Tconv = Sampling time + 12.5 cycles Example:... -
Page 172: Dma Request
Analog-to-digital converter (ADC) RM0041 The software source trigger events can be generated by setting a bit in a register (SWSTART and JSWSTART in ADC_CR2). A regular group conversion can be interrupted by an injected trigger. 10.8 DMA request Since converted regular channels value are stored in a unique data register, it is necessary to use DMA for conversion of more than one regular channel. -
Page 173: Figure 31. Temperature Sensor And Vrefint Channel Block Diagram
RM0041 Analog-to-digital converter (ADC) Figure 31. Temperature sensor and V channel block diagram REFINT TSVREFE control bit Temperature V SENSE sensor ADC1_IN16 Converted data ADC1 V REFINT Internal ADC1_IN17 power block MS35936V2 RM0041 Rev 6 173/709... -
Page 174: Adc Interrupts
Analog-to-digital converter (ADC) RM0041 Reading the temperature To use the sensor: Select the ADCx_IN16 input channel. Select a sample time of 17.1 µs Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake up the temperature sensor from power down mode. Start the ADC conversion by setting the ADON bit (or by external trigger). -
Page 175: Adc Registers
RM0041 Analog-to-digital converter (ADC) 10.11 ADC registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 10.11.1 ADC status register (ADC_SR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved STRT... -
Page 176: Adc Control Register 1 (Adc_Cr1)
Analog-to-digital converter (ADC) RM0041 10.11.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 AWDE JAWDE Reserved Reserved JDISCE DISC JEOC DISCNUM[2:0] JAUTO SCAN AWDIE EOCIE AWDCH[4:0] Bits 31:24 Reserved, must be kept at reset value. Bit 23 AWDEN: Analog watchdog enable on regular channels This bit is set/reset by software. -
Page 177: Adc Control Register 2 (Adc_Cr2)
RM0041 Analog-to-digital converter (ADC) Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode This bit set and cleared by software to enable/disable the analog watchdog on the channel identified by the AWDCH[4:0] bits. 0: Analog watchdog enabled on all channels 1: Analog watchdog enabled on a single channel Bit 8 SCAN: Scan mode This bit is set and cleared by software to enable/disable Scan mode. - Page 178 Analog-to-digital converter (ADC) RM0041 JEXTT JEXTSEL[2:0] ALIGN Reserved CONT ADON Reserved Res. Bits 31:24 Reserved, must be kept at reset value. Bit 23 TSVREFE: Temperature sensor and V enable REFINT This bit is set and cleared by software to enable/disable the temperature sensor and V REFINT channel.
- Page 179 RM0041 Analog-to-digital converter (ADC) Bits 14:12 JEXTSEL[2:0]: External event select for injected group These bits select the external event used to trigger the start of conversion of an injected group: 000: Timer 1 TRGO event 001: Timer 1 CC4 event 010: Timer 2 TRGO event 011: Timer 2 CC1 event 100: Timer 3 CC4 event...
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Page 180: Adc Sample Time Register 1 (Adc_Smpr1)
Analog-to-digital converter (ADC) RM0041 10.11.4 ADC sample time register 1 (ADC_SMPR1) Address offset: 0x0C Reset value: 0x0000 0000 SMP17[2:0] SMP16[2:0] SMP15[2:1] Reserved SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0] 15_0 Bits 31:24 Reserved, must be kept at reset value. Bits 23:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel. -
Page 181: Adc Sample Time Register 2 (Adc_Smpr2)
RM0041 Analog-to-digital converter (ADC) 10.11.5 ADC sample time register 2 (ADC_SMPR2) Address offset: 0x10 Reset value: 0x0000 0000 Reserved SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1] Res. SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel. -
Page 182: Adc Watchdog High Threshold Register (Adc_Htr)
Analog-to-digital converter (ADC) RM0041 10.11.7 ADC watchdog high threshold register (ADC_HTR) Address offset: 0x24 Reset value: 0x0000 0FFF Reserved HT[11:0] Reserved Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 HT[11:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: The software can write to these registers when an ADC conversion is ongoing. -
Page 183: Adc Regular Sequence Register 1 (Adc_Sqr1)
RM0041 Analog-to-digital converter (ADC) 10.11.9 ADC regular sequence register 1 (ADC_SQR1) Address offset: 0x2C Reset value: 0x0000 0000 L[3:0] SQ16[4:1] Reserved SQ16_0 SQ15[4:0] SQ14[4:0] SQ13[4:0] Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. -
Page 184: Adc Regular Sequence Register 2 (Adc_Sqr2)
Analog-to-digital converter (ADC) RM0041 10.11.10 ADC regular sequence register 2 (ADC_SQR2) Address offset: 0x30 Reset value: 0x0000 0000 SQ12[4:0] SQ11[4:0] SQ10[4:1] Reserved SQ10_ SQ9[4:0] SQ8[4:0] SQ7[4:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 12th in the sequence to be converted. -
Page 185: Adc Regular Sequence Register 3 (Adc_Sqr3)
RM0041 Analog-to-digital converter (ADC) 10.11.11 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x34 Reset value: 0x0000 0000 SQ6[4:0] SQ5[4:0] SQ4[4:1] Reserved SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 6th in the sequence to be converted. -
Page 186: Adc Injected Sequence Register (Adc_Jsqr)
Analog-to-digital converter (ADC) RM0041 10.11.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 JL[1:0] JSQ4[4:1] Reserved JSQ4_0 JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. -
Page 187: Adc Injected Data Register X (Adc_Jdrx) (X= 1
RM0041 Analog-to-digital converter (ADC) 10.11.13 ADC injected data register x (ADC_JDRx) (x= 1..4) Address offset: 0x3C - 0x48 Reset value: 0x0000 0000 Reserved JDATA[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read only. They contain the conversion result from injected channel x. The data is left or right-aligned as shown in Figure 29 Figure... -
Page 188: 10.11.15 Adc Register Map
Analog-to-digital converter (ADC) RM0041 10.11.15 ADC register map The following table summarizes the ADC registers. Table 62. ADC register map and reset values Offset Register ADC_SR 0x00 Reserved Reset value DISC ADC_CR1 AWDCH[4:0] 0x04 Reserved Reserved [2:0] Reset value JEXTSE EXTSEL ADC_CR2 [2:0]... - Page 189 RM0041 Analog-to-digital converter (ADC) Table 62. ADC register map and reset values (continued) Offset Register SQ12[4:0] 12th SQ11[4:0] 11th SQ10[4:0] 10th SQ9[4:0] 9th SQ8[4:0] 8th SQ7[4:0] 7th conversion in conversion in conversion in conversion in conversion in conversion in ADC_SQR2 regular regular regular...
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Page 190: Digital-To-Analog Converter (Dac)
Digital-to-analog converter (DAC) RM0041 Digital-to-analog converter (DAC) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 191: Table 63. Dac Pins
RM0041 Digital-to-analog converter (DAC) Figure 32. DAC channel block diagram DAC control register TSELx[2:0] bits SWTR IGx TIM6_T RGO DMAENx TIM7_T RGO TIM3_T RGO TIM2_T RGO TIM4_T RGO TIM5_TRGO or TIM15_TRGO EXTI_9 DM A req ue stx Control logicx TENx 12-bit DHRx MAMPx[3:0] bits... -
Page 192: Dac Functional Description
Digital-to-analog converter (DAC) RM0041 11.3 DAC functional description 11.3.1 DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time t WAKEUP Note: The ENx bit enables the analog DAC Channelx macrocell only. -
Page 193: Dac Conversion
RM0041 Digital-to-analog converter (DAC) Figure 33. Data registers in single DAC channel mode 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710b • Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits) –... -
Page 194: Dac Output Voltage
Digital-to-analog converter (DAC) RM0041 When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time t that depends on the power supply voltage and the SETTLING analog output load. Figure 35. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK 0x1AC Output voltage... -
Page 195: Dma Request
RM0041 Digital-to-analog converter (DAC) If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents. Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle. -
Page 196: Triangle-Wave Generation
Digital-to-analog converter (DAC) RM0041 Figure 36. DAC LFSR register calculation algorithm ai14713c The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register. -
Page 197: Dual Dac Channel Conversion
RM0041 Digital-to-analog converter (DAC) It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits. Figure 38. DAC triangle wave generation MAMPx[3:0] max amplitude + DAC_DHRx base value DAC_DHRx base value ai14715c Figure 39. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK 0x00 0xD55... -
Page 198: Independent Trigger Without Wave Generation
Digital-to-analog converter (DAC) RM0041 11.4.1 Independent trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •... -
Page 199: Independent Trigger With Single Triangle Generation
RM0041 Digital-to-analog converter (DAC) 11.4.4 Independent trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •... -
Page 200: Simultaneous Trigger Without Wave Generation
Digital-to-analog converter (DAC) RM0041 11.4.7 Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •... -
Page 201: Simultaneous Trigger With Single Triangle Generation
RM0041 Digital-to-analog converter (DAC) 11.4.10 Simultaneous trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •... -
Page 202: Dac Registers
Digital-to-analog converter (DAC) RM0041 11.5 DAC registers Refer to Section 1.1: List of abbreviations for registers for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32 bits). 11.5.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 DMAU... - Page 203 RM0041 Digital-to-analog converter (DAC) Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event 001: Timer 3 TRGO event 010: Timer 7 TRGO event 011: Timer 5 or timer 15 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9...
- Page 204 Digital-to-analog converter (DAC) RM0041 Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
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Page 205: Dac Software Trigger Register (Dac_Swtrigr)
RM0041 Digital-to-analog converter (DAC) 11.5.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Reserved SWTRIG2 SWTRIG1 Reserved Bits 31:2 Reserved, must be kept at reset value. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set and cleared by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2... -
Page 206: Dac Channel1 12-Bit Left Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0041 11.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Reserved DACC1DHR[11:0] Reserved Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. -
Page 207: Dac Channel2 12-Bit Right Aligned Data Holding Register
RM0041 Digital-to-analog converter (DAC) 11.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 Reserved DACC2DHR[11:0] Reserved Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. -
Page 208: Dual Dac 12-Bit Right-Aligned Data Holding Register (Dac_Dhr12Rd)
Digital-to-analog converter (DAC) RM0041 11.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. -
Page 209: Dual Dac 8-Bit Right Aligned Data Holding Register
RM0041 Digital-to-analog converter (DAC) 11.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 Reserved DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. -
Page 210: Dac Status Register (Dac_Sr)
Digital-to-analog converter (DAC) RM0041 11.5.14 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 DMAUDR2 Reserved Reserved rc_w1 DMAUDR1 Reserved Reserved rc_w1 Bits 31:30 Reserved, must be kept at reset value. Bit 29 DMAUDR2: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). - Page 211 RM0041 Digital-to-analog converter (DAC) Table 65. DAC register map (continued) Offset Register DAC_ 0x1C Reserved DACC2DHR[7:0] DHR8R2 DAC_ 0x20 Reserved DACC2DHR[11:0] Reserved DACC1DHR[11:0] DHR12RD DAC_ 0x24 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved DHR12LD DAC_ 0x28 Reserved DACC2DHR[7:0] DACC1DHR[7:0] DHR8RD DAC_ 0x2C Reserved DACC1DOR[11:0] DOR1 DAC_...
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Page 212: Advanced-Control Timer (Tim1)
Advanced-control timer (TIM1) RM0041 Advanced-control timer (TIM1) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 213: Tim1 Main Features
RM0041 Advanced-control timer (TIM1) 12.2 TIM1 main features TIM1 timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536. •... -
Page 214: Figure 40. Advanced-Control Timer Block Diagram
Advanced-control timer (TIM1) RM0041 Figure 40. Advanced-control timer block diagram Internal clock (CK_INT) CK_TIM18 from RCC Trigger Polarity selection, ETRF controller Edge detector and Prescaler ETRP TRGO To other timers To DAC and ADC Input filter ITR0 ITR1 TRGI ITR2 Slave mode controller ITR3... -
Page 215: Tim1 Functional Description
RM0041 Advanced-control timer (TIM1) 12.3 TIM1 functional description 12.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler. -
Page 216: Figure 41. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Advanced-control timer (TIM1) RM0041 Figure 41. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 42. -
Page 217: Counter Modes
RM0041 Advanced-control timer (TIM1) 12.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1). -
Page 218: Figure 44. Counter Timing Diagram, Internal Clock Divided By 2
Advanced-control timer (TIM1) RM0041 Figure 44. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V3 Figure 45. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT... -
Page 219: Figure 47. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded)
RM0041 Advanced-control timer (TIM1) Figure 47. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V3 Figure 48. - Page 220 Advanced-control timer (TIM1) RM0041 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
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Page 221: Figure 49. Counter Timing Diagram, Internal Clock Divided By 1
RM0041 Advanced-control timer (TIM1) Figure 49. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 01 00 34 33 32 Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) MS31184V1 Figure 50. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT... -
Page 222: Figure 51. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timer (TIM1) RM0041 Figure 51. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0036 0035 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS40510V1 Figure 52. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register... -
Page 223: Figure 53. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
RM0041 Advanced-control timer (TIM1) Figure 53. Counter timing diagram, update event when repetition counter is not used CK_PSC Timerclock = CK_CNT 30 2F Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31188V1 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the... -
Page 224: Figure 54. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timer (TIM1) RM0041 When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The repetition counter is reloaded with the content of TIMx_RCR register •... -
Page 225: Figure 56. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
RM0041 Advanced-control timer (TIM1) Figure 56. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT 0034 0035 0036 0035 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31191V2 Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 57. -
Page 226: Repetition Counter
Advanced-control timer (TIM1) RM0041 Figure 58. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC Timer clock = CK_CNT Counter register 04 03 02 03 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active register MS31193V3... -
Page 227: Figure 60. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
RM0041 Advanced-control timer (TIM1) The repetition counter is decremented: • At each counter overflow in upcounting mode, • At each counter underflow in downcounting mode, • At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period. -
Page 228: Clock Selection
Advanced-control timer (TIM1) RM0041 12.3.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, the user can configure Timer 1 to act as a prescaler for Timer 2. -
Page 229: Figure 62. Ti2 External Clock Connection Example
RM0041 Advanced-control timer (TIM1) Figure 62. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F TI1F Encoder ITRx mode TI1_ED TRGI External clock TI1FP1 CK_PSC mode 1 TI2F_Rising Edge TI2FP2 External clock ETRF Filter detector mode 2 ETRF TI2F_Falling CK_INT Internal clock mode (internal clock) ICF[3:0]... -
Page 230: Figure 63. Control Circuit In External Clock Mode 1
Advanced-control timer (TIM1) RM0041 Figure 63. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 MS31087V2 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. -
Page 231: Capture/Compare Channels
RM0041 Advanced-control timer (TIM1) For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. -
Page 232: Figure 66. Capture/Compare Channel (Example: Channel 1 Input Stage)
Advanced-control timer (TIM1) RM0041 Figure 66. Capture/compare channel (example: channel 1 input stage) TI1F_ED To the slave mode controller TI1F_Rising TI1FP1 Filter TI1F Edge TI1F_Falling downcounter detector IC1PS Divider TI2FP1 /1, /2, /4, /8 CC1P/CC1NP ICF[3:0] TIMx_CCER TIMx_CCMR1 (from slave mode controller) TI2F_Rising (from channel 2) -
Page 233: Figure 68. Output Stage Of Capture/Compare Channel (Channel 1 To 3)
RM0041 Advanced-control timer (TIM1) Figure 68. Output stage of capture/compare channel (channel 1 to 3) To the master mode controller ETRF Output enable ‘0’ circuit OC1REFC OC1REF OC1_DT CC1P CNT>CCR1 Output Output Dead-time TIM1_CCER mode CNT=CCR1 selector generator controller OC1N_DT Output OC1N ‘0’... -
Page 234: Input Capture Mode
Advanced-control timer (TIM1) RM0041 12.3.6 Input capture mode In Input capture mode, the Capture/Compare registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. -
Page 235: Pwm Input Mode
RM0041 Advanced-control timer (TIM1) 12.3.7 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •... -
Page 236: Output Compare Mode
Advanced-control timer (TIM1) RM0041 forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. -
Page 237: Pwm Mode
RM0041 Advanced-control timer (TIM1) Figure 71. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIM1_CNT 0039 003A 003B B200 B201 TIM1_CCR1 003A B201 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V2 12.3.10 PWM mode Pulse Width Modulation mode allows generating a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. -
Page 238: Figure 72. Edge-Aligned Pwm Waveforms (Arr=8)
Advanced-control timer (TIM1) RM0041 compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 72 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8. -
Page 239: Figure 73. Center-Aligned Pwm Waveforms (Arr=8)
RM0041 Advanced-control timer (TIM1) TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting). Figure 73 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, •... -
Page 240: Complementary Outputs And Dead-Time Insertion
Advanced-control timer (TIM1) RM0041 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. -
Page 241: Figure 74. Complementary Output With Dead-Time Insertion
RM0041 Advanced-control timer (TIM1) Figure 74. Complementary output with dead-time insertion. OCxREF delay OCxN delay MS31095V1 Figure 75. Dead-time waveforms with delay greater than the negative pulse. OCxREF delay OCxN MS31096V1 Figure 76. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay... -
Page 242: Using The Break Function
Advanced-control timer (TIM1) RM0041 have both outputs at inactive level or both outputs active and complementary with dead-time. Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low. - Page 243 RM0041 Advanced-control timer (TIM1) active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
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Page 244: Figure 77. Output Behavior In Response To A Break
Advanced-control timer (TIM1) RM0041 Figure 77 shows an example of behavior of the outputs in response to a break. Figure 77. Output behavior in response to a break. BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay... -
Page 245: Clearing The Ocxref Signal On An External Event
RM0041 Advanced-control timer (TIM1) 12.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs. -
Page 246: 6-Step Pwm Generation
Advanced-control timer (TIM1) RM0041 12.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. The user can thus program in advance the configuration for the next step and change the configuration of all the channels at the same time. -
Page 247: One-Pulse Mode
RM0041 Advanced-control timer (TIM1) 12.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. -
Page 248: Encoder Interface Mode
Advanced-control timer (TIM1) RM0041 auto-reload value. To do this, enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. The user can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case the compare value must be written in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. -
Page 249: Table 66. Counting Direction Versus Encoder Signals
RM0041 Advanced-control timer (TIM1) Table 66 summarizes the possible combinations, assuming TI1 and TI2 do not switch at the same time. Table 66. Counting direction versus encoder signals TI1FP1 signal TI2FP2 signal Active Level on opposite signal edge (TI1FP1 for TI2, TI2FP2 for TI1) Rising Falling Rising... -
Page 250: Figure 81. Example Of Counter Operation In Encoder Interface Mode
Advanced-control timer (TIM1) RM0041 Figure 81. Example of counter operation in encoder interface mode. forward jitter backward jitter forward Counter down MS33107V1 Figure 82 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 82. -
Page 251: Timer Input Xor Function
RM0041 Advanced-control timer (TIM1) 12.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3. -
Page 252: Figure 83. Example Of Hall Sensor Interface
Advanced-control timer (TIM1) RM0041 Figure 83 describes this example. Figure 83. Example of Hall sensor interface TIH1 TIH2 TIH3 counter (CNT) (CCR2) CCR1 C7A3 C7A8 C794 C7A5 C7AB C796 TRGO=OC2REF OC1N OC2N OC3N Write CCxE, CCxNE and OCxM for next step ai17336 252/709 RM0041 Rev 6... -
Page 253: Timx And External Trigger Synchronization
RM0041 Advanced-control timer (TIM1) 12.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. -
Page 254: Figure 85. Control Circuit In Gated Mode
Advanced-control timer (TIM1) RM0041 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). -
Page 255: Figure 86. Control Circuit In Trigger Mode
RM0041 Advanced-control timer (TIM1) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). -
Page 256: Timer Synchronization
Advanced-control timer (TIM1) RM0041 – CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edge only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. A rising edge on TI1 enables the counter and sets the TIF flag. -
Page 257: Tim1 Registers
RM0041 Advanced-control timer (TIM1) 12.4 TIM1 registers Refer to Section 2.2 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 12.4.1 TIM1 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 CKD[1:0] ARPE... -
Page 258: Tim1 Control Register 2 (Timx_Cr2)
Advanced-control timer (TIM1) RM0041 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –... - Page 259 RM0041 Advanced-control timer (TIM1) Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
- Page 260 Advanced-control timer (TIM1) RM0041 Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output.
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Page 261: Tim1 Slave Mode Control Register (Timx_Smcr)
RM0041 Advanced-control timer (TIM1) 12.4.3 TIM1 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Res. Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. - Page 262 Advanced-control timer (TIM1) RM0041 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
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Page 263: Tim1 Dma/Interrupt Enable Register (Timx_Dier)
RM0041 Advanced-control timer (TIM1) Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control register description. - Page 264 Advanced-control timer (TIM1) RM0041 Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled 1: CC4 DMA request enabled Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled...
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Page 265: Tim1 Status Register (Timx_Sr)
RM0041 Advanced-control timer (TIM1) 12.4.5 TIM1 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC4OF CC3OF CC2OF CC1OF Res. COMIF CC4IF CC3IF CC2IF CC1IF Reserved rc_w0 rc_w0 rc_w0 rc_w0 Res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:13 Reserved, must be kept at reset value. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag... -
Page 266: Tim1 Event Generation Register (Timx_Egr)
Advanced-control timer (TIM1) RM0041 Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). - Page 267 RM0041 Advanced-control timer (TIM1) Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output.
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Page 268: Tim1 Capture/Compare Mode Register 1 (Timx_Ccmr1)
Advanced-control timer (TIM1) RM0041 12.4.7 TIM1 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. - Page 269 RM0041 Advanced-control timer (TIM1) Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
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Page 270: Tim1 Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timer (TIM1) RM0041 Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1... - Page 271 RM0041 Advanced-control timer (TIM1) Reset value: 0x0000 Refer to the above CCMR1 register description. OC4M[2:0] OC3M[2:0] CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable Bits 9:8 CC4S: Capture/Compare 4 selection...
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Page 272: Tim1 Capture/Compare Enable Register (Timx_Ccer)
Advanced-control timer (TIM1) RM0041 Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3... - Page 273 RM0041 Advanced-control timer (TIM1) Bit 8 CC3E: Capture/Compare 3 output enable refer to CC1E description Bit 7 CC2NP: Capture/Compare 2 complementary output polarity refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description...
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Page 274: Tim1 Counter (Timx_Cnt)
Advanced-control timer (TIM1) RM0041 Table 68. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not driven by Output Disabled (not driven by the the timer), OCx=0, OCx_EN=0 timer), OCxN=0, OCxN_EN=0 Output Disabled (not driven by... -
Page 275: Tim1 Auto-Reload Register (Timx_Arr)
RM0041 Advanced-control timer (TIM1) Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). -
Page 276: Tim1 Repetition Counter Register (Timx_Rcr)
Advanced-control timer (TIM1) RM0041 12.4.13 TIM1 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 REP[7:0] Reserved Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. -
Page 277: Tim1 Capture/Compare Register 2 (Timx_Ccr2)
RM0041 Advanced-control timer (TIM1) 12.4.15 TIM1 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). -
Page 278: Tim1 Capture/Compare Register 4 (Timx_Ccr4)
Advanced-control timer (TIM1) RM0041 12.4.17 TIM1 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). - Page 279 RM0041 Advanced-control timer (TIM1) Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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Page 280: Tim1 Dma Control Register (Timx_Dcr)
Advanced-control timer (TIM1) RM0041 Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>... -
Page 281: Tim1 Dma Address For Full Transfer (Timx_Dmar)
RM0041 Advanced-control timer (TIM1) 12.4.20 TIM1 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 0000 DMAB[31:16] DMAB[15:0] Bits 31:0 DMAB[31:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the... -
Page 282: Tim1 Register Map
Advanced-control timer (TIM1) RM0041 12.4.21 TIM1 register map TIM1 registers are mapped as 16-bit addressable registers as described in the table below: Table 69. TIM1 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reserved Reset value TIMx_CR2 MMS[2:0] 0x04 Reserved... - Page 283 RM0041 Advanced-control timer (TIM1) Table 69. TIM1 register map and reset values (continued) Offset Register TIMx_ARR ARR[15:0] 0x2C Reserved Reset value TIMx_RCR REP[7:0] 0x30 Reserved Reset value TIMx_CCR1 CCR1[15:0] 0x34 Reserved Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reserved Reset value TIMx_CCR3 CCR3[15:0] 0x3C Reserved...
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Page 284: General-Purpose Timers (Tim2 To Tim5)
General-purpose timers (TIM2 to TIM5) RM0041 General-purpose timers (TIM2 to TIM5) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 285: Tim2 To Tim5 Main Features
RM0041 General-purpose timers (TIM2 to TIM5) 13.2 TIM2 to TIM5 main features General-purpose TIMx timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536. •... -
Page 286: Tim2 To Tim5 Functional Description
General-purpose timers (TIM2 to TIM5) RM0041 Figure 88. General-purpose timer block diagram Internal clock (CK_INT) TIMxCLK from RCC ETRF ETRP Polarity selection & edge TIMx_ETR Input filter detector & prescaler TRGO ITR0 Trigger to other timers ITR1 controller to DAC/ADC ITR2 TRGI Slave... -
Page 287: Figure 89. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0041 General-purpose timers (TIM2 to TIM5) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. -
Page 288: Counter Modes
General-purpose timers (TIM2 to TIM5) RM0041 Figure 90. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register F8 F9 FA FB Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS35834V1... -
Page 289: Figure 91. Counter Timing Diagram, Internal Clock Divided By 1
RM0041 General-purpose timers (TIM2 to TIM5) Figure 91. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timerclock = CK_CNT Counter register 35 36 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS35836V1 Figure 92. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timerclock = CK_CNT... -
Page 290: Figure 94. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2 to TIM5) RM0041 Figure 94. Counter timing diagram, internal clock divided by N CK_INT Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MSv37302V1 Figure 95. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN... -
Page 291: Figure 96. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
RM0041 General-purpose timers (TIM2 to TIM5) Figure 96. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register... -
Page 292: Figure 97. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM2 to TIM5) RM0041 Figure 97. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timerclock = CK_CNT Counter register 04 03 02 01 00 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) MSv37305V1 Figure 98. -
Page 293: Figure 100. Counter Timing Diagram, Internal Clock Divided By N
RM0041 General-purpose timers (TIM2 to TIM5) Figure 100. Counter timing diagram, internal clock divided by N CK_INT Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS37340V1 Figure 101. Counter timing diagram, Update event CK_INT CNT_EN Timerclock = CK_CNT Counter register... -
Page 294: Figure 102. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
General-purpose timers (TIM2 to TIM5) RM0041 In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. -
Page 295: Figure 103. Counter Timing Diagram, Internal Clock Divided By 2
RM0041 General-purpose timers (TIM2 to TIM5) Figure 103. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timerclock = CK_CNT Counter register 0003 0002 0001 0000 0001 0002 0003 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS37343V1 Figure 104. -
Page 296: Figure 106. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow)
General-purpose timers (TIM2 to TIM5) RM0041 Figure 106. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_INT CNT_EN Timerclock = CK_CNT Counter register 05 04 03 02 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active register... -
Page 297: Clock Selection
RM0041 General-purpose timers (TIM2 to TIM5) 13.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) • External clock mode2: external trigger input (ETR). •... -
Page 298: Figure 109. Ti2 External Clock Connection Example
General-purpose timers (TIM2 to TIM5) RM0041 Figure 109. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F TI1F Encoder ITRx mode TI1_ED TRGI External clock TI1FP1 CK_PSC mode 1 TI2F_Rising Edge TI2FP2 External clock ETRF Filter detector mode 2 ETRF TI2F_Falling CK_INT Internal clock mode... -
Page 299: Figure 110. Control Circuit In External Clock Mode 1
RM0041 General-purpose timers (TIM2 to TIM5) Figure 110. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 MS31087V2 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. -
Page 300: Capture/Compare Channels
General-purpose timers (TIM2 to TIM5) RM0041 The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 112. Control circuit in external clock mode 2 CK_INT CNT_EN ETRP... -
Page 301: Figure 114. Capture/Compare Channel 1 Main Circuit
RM0041 General-purpose timers (TIM2 to TIM5) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 114. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H Read CCR1H... -
Page 302: Input Capture Mode
General-purpose timers (TIM2 to TIM5) RM0041 13.3.5 Input capture mode In Input capture mode, the Capture/Compare registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. -
Page 303: Pwm Input Mode
RM0041 General-purpose timers (TIM2 to TIM5) 13.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •... -
Page 304: Forced Output Mode
General-purpose timers (TIM2 to TIM5) RM0041 13.3.7 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. -
Page 305: Pwm Mode
RM0041 General-purpose timers (TIM2 to TIM5) The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 117. -
Page 306: Figure 118. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2 to TIM5) RM0041 The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode. -
Page 307: Figure 119. Center-Aligned Pwm Waveforms (Arr=8)
RM0041 General-purpose timers (TIM2 to TIM5) up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting). Figure 119 shows some center-aligned PWM waveforms in an example where: •... -
Page 308: One-Pulse Mode
General-purpose timers (TIM2 to TIM5) RM0041 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. -
Page 309: Clearing The Ocxref Signal On An External Event
RM0041 General-purpose timers (TIM2 to TIM5) Let’s use TI2FP2 as trigger 1: • Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=0 in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register. -
Page 310: Encoder Interface Mode
General-purpose timers (TIM2 to TIM5) RM0041 The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs. -
Page 311: Table 70. Counting Direction Versus Encoder Signals
RM0041 General-purpose timers (TIM2 to TIM5) must configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. -
Page 312: Figure 122. Example Of Counter Operation In Encoder Interface Mode
General-purpose timers (TIM2 to TIM5) RM0041 Figure 122. Example of counter operation in encoder interface mode forward jitter backward jitter forward Counter down MS33107V1 Figure 123 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 123. -
Page 313: Timer Input Xor Function
RM0041 General-purpose timers (TIM2 to TIM5) 13.3.13 Timer input XOR function The TI1S bit in the TIM1_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture. -
Page 314: Figure 125. Control Circuit In Gated Mode
General-purpose timers (TIM2 to TIM5) RM0041 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, no need of any filter, IC1F=0000 kept). -
Page 315: Figure 126. Control Circuit In Trigger Mode
RM0041 General-purpose timers (TIM2 to TIM5) When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. -
Page 316: Timer Synchronization
General-purpose timers (TIM2 to TIM5) RM0041 Figure 127. Control circuit in external clock mode 2 + trigger mode CEN/CNT_EN Counter clock = CK_CNT = CK_PSC Counter register MS33110V1 13.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master mode, it can reset, start, stop or clock the counter of another Timer configured in Slave mode. -
Page 317: Figure 129. Gating Tim2 With Oc1Ref Of Tim3
RM0041 General-purpose timers (TIM2 to TIM5) For example, the user can configure TIM3 to act as a prescaler for TIM2. Refer to Figure 128. To do this: • Configure TIM3 in master mode so that it outputs a periodic trigger signal on each update event UEV. -
Page 318: Figure 130. Gating Tim2 With Enable Of Tim3
General-purpose timers (TIM2 to TIM5) RM0041 value by resetting both timers before starting TIM3. The user can then write any value in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers. In the next example, we synchronize TIM3 and TIM2. -
Page 319: Figure 131. Triggering Tim2 With Update Of Tim3
RM0041 General-purpose timers (TIM2 to TIM5) counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f /3). CK_CNT CK_INT • Configure TIM3 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM3_CR2 register). -
Page 320: Debug Mode
General-purpose timers (TIM2 to TIM5) RM0041 Starting 2 timers synchronously in response to an external trigger In this example, we set the enable of TIM3 when its TI1 input rises, and the enable of TIM2 with the enable of TIM3. Refer to Figure 128 for connections. -
Page 321: Timx2 To Tim5 Registers
RM0041 General-purpose timers (TIM2 to TIM5) 13.4 TIMx2 to TIM5 registers Refer to Section 2.2 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). - Page 322 General-purpose timers (TIM2 to TIM5) RM0041 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
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Page 323: Timx Control Register 2 (Timx_Cr2)
RM0041 General-purpose timers (TIM2 to TIM5) 13.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 TI1S MMS[2:0] CCDS Reserved Reserved Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section 12.3.18: Interfacing with Hall sensors... -
Page 324: Timx Slave Mode Control Register (Timx_Smcr)
General-purpose timers (TIM2 to TIM5) RM0041 13.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] OCCS SMS[2:0] Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable... - Page 325 RM0041 General-purpose timers (TIM2 to TIM5) Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
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Page 326: Timx Dma/Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM2 to TIM5) RM0041 Table 71. TIMx internal trigger connection Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM2 TIM1 TIM15 TIM3 TIM4 TIM3 TIM1 TIM2 TIM15 TIM4 TIM4 TIM1 TIM2... -
Page 327: Timx Status Register (Timx_Sr)
RM0041 General-purpose timers (TIM2 to TIM5) Bit 3 CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled 1: CC3 interrupt enabled Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable... - Page 328 General-purpose timers (TIM2 to TIM5) RM0041 Bit 3 CC3IF: Capture/Compare 3 interrupt flag refer to CC1IF description Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
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Page 329: Timx Event Generation Register (Timx_Egr)
RM0041 General-purpose timers (TIM2 to TIM5) 13.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 CC4G CC3G CC2G CC1G Reserved Res. Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. -
Page 330: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
General-purpose timers (TIM2 to TIM5) RM0041 13.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. - Page 331 RM0041 General-purpose timers (TIM2 to TIM5) Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
- Page 332 General-purpose timers (TIM2 to TIM5) RM0041 Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
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Page 333: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
RM0041 General-purpose timers (TIM2 to TIM5) 13.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode... -
Page 334: Timx Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM2 to TIM5) RM0041 Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3... -
Page 335: Timx Counter (Timx_Cnt)
RM0041 General-purpose timers (TIM2 to TIM5) Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bits 3:2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high. 1: OC1 active low. -
Page 336: Timx Auto-Reload Register (Timx_Arr)
General-purpose timers (TIM2 to TIM5) RM0041 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). -
Page 337: Timx Capture/Compare Register 2 (Timx_Ccr2)
RM0041 General-purpose timers (TIM2 to TIM5) 13.4.14 TIMx capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). -
Page 338: Timx Dma Control Register (Timx_Dcr)
General-purpose timers (TIM2 to TIM5) RM0041 Bits 15:0 CCR4[15:0]: Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). - Page 339 RM0041 General-purpose timers (TIM2 to TIM5) Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
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Page 340: Timx Register Map
General-purpose timers (TIM2 to TIM5) RM0041 13.4.19 TIMx register map TIMx registers are mapped as described in the table below: Table 73. TIMx register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reserved Reset value TIMx_CR2 [2:0] 0x04 Reserved Reset value ETPS... - Page 341 RM0041 General-purpose timers (TIM2 to TIM5) Table 73. TIMx register map and reset values (continued) Offset Register TIMx_CNT CNT[15:0] 0x24 Reserved Reset value TIMx_PSC PSC[15:0] 0x28 Reserved Reset value TIMx_ARR ARR[15:0] 0x2C Reserved Reset value 0x30 Reserved TIMx_CCR1 CCR1[15:0] 0x34 Reserved Reset value TIMx_CCR2...
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Page 342: General-Purpose Timers (Tim12/13/14)
General-purpose timers (TIM12/13/14) RM0041 General-purpose timers (TIM12/13/14) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 Kbytes and 1 Mbyte. -
Page 343: Tim13/Tim14 Main Features
RM0041 General-purpose timers (TIM12/13/14) Figure 134. General-purpose timer block diagram (TIM12) Internal clock (CK_INT) Trigger controller ITR0 Slave ITR1 Reset, enable, up, count controller ITR2 TRGI mode ITR3 TI1F_ED TI1FP1 TI2FP2 Auto-reload register Stop, Clear CK_PSC CK_CNT CNT counter prescaler CC1I CC1I TI1FP1... -
Page 344: Figure 135. General-Purpose Timer Block Diagram (Tim13/14)
General-purpose timers (TIM12/13/14) RM0041 Figure 135. General-purpose timer block diagram (TIM13/14) Internal clock (CK_INT) Enable Trigger counter Controller Autoreload register Stop, Clear CK_PSC CK_CNT prescaler counter CC1I CC1I TI1FP1 output Input filter & IC1PS OC1REF Prescaler Capture/Compare 1 register TIMx_CH1 TIMx_CH1 edge detector control... -
Page 345: Tim12/13/14 Functional Description
RM0041 General-purpose timers (TIM12/13/14) 14.3 TIM12/13/14 functional description 14.3.1 Time-base unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. -
Page 346: Figure 136. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM12/13/14) RM0041 Figure 136. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 137. -
Page 347: Counter Modes
RM0041 General-purpose timers (TIM12/13/14) 14.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM12) also generates an update event. -
Page 348: Figure 139. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM12/13/14) RM0041 Figure 139. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V3 Figure 140. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT... -
Page 349: Figure 142. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded)
RM0041 General-purpose timers (TIM12/13/14) Figure 142. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V3 Figure 143. -
Page 350: Clock Selection
General-purpose timers (TIM12/13/14) RM0041 14.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1 (for TIM12): external input pin (TIx) • Internal trigger inputs (ITRx) (for TIM12): connecting the trigger output from another timer. -
Page 351: Figure 145. Ti2 External Clock Connection Example
RM0041 General-purpose timers (TIM12/13/14) Figure 145. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F TI1F ITRx TI1_ED CK_PSC TRGI External clock TI1FP1 mode 1 TI2F_Rising Edge TI2FP2 Filter detector TI2F_Falling CK_INT Internal clock mode (internal clock) ICF[3:0] CC2P TIMx_CCER TIMx_CCMR1 SMS[2:0] TIMx_SMCR MS37337V1... -
Page 352: Capture/Compare Channels
General-purpose timers (TIM12/13/14) RM0041 14.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 147 Figure 149 give an overview of a capture/compare channel. -
Page 353: Input Capture Mode
RM0041 General-purpose timers (TIM12/13/14) Figure 148. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H Read CCR1H write_in_progress read_in_progress write CCR1L Capture/compare preload register Read CCR1L Output CC1S[1] compare_transfer capture_transfer mode CC1S[0] Input CC1S[1] OC1PE mode OC1PE Capture /compare shadow register CC1S[0] TIMx_CCMR1 (from time... - Page 354 General-purpose timers (TIM12/13/14) RM0041 cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when the user writes it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises.
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Page 355: Pwm Input Mode (Only For Tim12)
RM0041 General-purpose timers (TIM12/13/14) 14.3.6 PWM input mode (only for TIM12) This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •... -
Page 356: Forced Output Mode
General-purpose timers (TIM12/13/14) RM0041 14.3.7 Forced output mode In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, the user just needs to write ‘101’... -
Page 357: Pwm Mode
RM0041 General-purpose timers (TIM12/13/14) The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 151. -
Page 358: One-Pulse Mode
General-purpose timers (TIM12/13/14) RM0041 TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 152 shows some edge- aligned PWM waveforms in an example where TIMx_ARR=8. Figure 152. -
Page 359: Figure 153. Example Of One Pulse Mode
RM0041 General-purpose timers (TIM12/13/14) Figure 153. Example of one pulse mode. OC1REF TIM1_ARR TIM1_CCR1 DELAY PULSE MS31099V1 For example the user may want to generate a positive pulse on OC1 with a length of t PULSE and after a delay of t as soon as a positive edge is detected on the TI2 input pin. -
Page 360: Tim12 External Trigger Synchronization
General-purpose timers (TIM12/13/14) RM0041 Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay t min we can get. -
Page 361: Figure 154. Control Circuit In Reset Mode
RM0041 General-purpose timers (TIM12/13/14) Figure 154. Control circuit in reset mode Counter clock = ck_cnt = ck_psc Counter register 32 33 34 35 36 01 02 03 00 01 02 03 MS31401V2 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1. -
Page 362: Figure 155. Control Circuit In Gated Mode
General-purpose timers (TIM12/13/14) RM0041 Figure 155. Control circuit in gated mode cnt_en Counter clock = ck_cnt = ck_psc Counter register 32 33 35 36 Write TIF=0 MS31402V1 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2. -
Page 363: Timer Synchronization (Tim12)
RM0041 General-purpose timers (TIM12/13/14) 14.3.12 Timer synchronization (TIM12) The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 13.3.15: Timer synchronization for details. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. -
Page 364: Tim12 Registers
General-purpose timers (TIM12/13/14) RM0041 14.4 TIM12 registers Refer to Section 2.2 for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 14.4.1 TIM12 control register 1 (TIMx_CR1) Address offset: 0x00... -
Page 365: Tim12 Control Register 2 (Timx_Cr2)
RM0041 General-purpose timers (TIM12/13/14) 14.4.2 TIM12 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 MMS[2:0] Reserved Reserved Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS[2:0]: Master mode selection These bits are used to select the information to be sent in Master mode to slave timers for synchronization (TRGO). -
Page 366: Tim12 Slave Mode Control Register (Timx_Smcr)
General-purpose timers (TIM12/13/14) RM0041 14.4.3 TIM12 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 TS[2:0] SMS[2:0] Reserved Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). -
Page 367: Tim12 Interrupt Enable Register (Timx_Dier)
RM0041 General-purpose timers (TIM12/13/14) Bit 3 Reserved, must be kept at reset value. Bits 2:0 SMS: Slave mode selection When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input control register and Control register descriptions. - Page 368 General-purpose timers (TIM12/13/14) RM0041 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled.
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Page 369: Tim12 Status Register (Timx_Sr)
RM0041 General-purpose timers (TIM12/13/14) 14.4.5 TIM12 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC2OF CC1OF CC2IF CC1IF Reserved Reserved Reserved rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input... -
Page 370: Tim Event Generation Register (Timx_Egr)
General-purpose timers (TIM12/13/14) RM0041 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –... -
Page 371: Tim Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0041 General-purpose timers (TIM12/13/14) 14.4.7 TIM capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits in this register have different functions in input and output modes. - Page 372 General-purpose timers (TIM12/13/14) RM0041 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N depend on the CC1P and CC1NP bits, respectively.
- Page 373 RM0041 General-purpose timers (TIM12/13/14) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
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Page 374: Tim12 Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM12/13/14) RM0041 14.4.8 TIM12 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 CC2NP CC2P CC2E CC1NP CC1P CC1E Reserved Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bits 6 Reserved, must be kept at reset value. -
Page 375: Tim12 Counter (Timx_Cnt)
RM0041 General-purpose timers (TIM12/13/14) Table 75. Output control bit for standard OCx channels CCxE bit OCx output state Output disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers. -
Page 376: Tim12 Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM12/13/14) RM0041 14.4.12 TIM12 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). -
Page 377: Tim12 Register Map
RM0041 General-purpose timers (TIM12/13/14) 14.4.14 TIM12 register map TIM12 registers are mapped as 16-bit addressable registers as described below. The reserved memory areas are highlighted in gray in the table. Table 76. TIM12 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00... - Page 378 General-purpose timers (TIM12/13/14) RM0041 Table 76. TIM12 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reserved Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reserved Reset value 0x3C to Reserved 0x4C Refer to for the register boundary addresses. 378/709 RM0041 Rev 6...
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Page 379: Tim13/14 Registers
RM0041 General-purpose timers (TIM12/13/14) 14.5 TIM13/14 registers The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 14.5.1 TIM13/14 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 CKD[1:0]... -
Page 380: Tim10/11/13/14 Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM12/13/14) RM0041 14.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 CC1IE Reserved Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled... -
Page 381: Tim13/14 Event Generation Register (Timx_Egr)
RM0041 General-purpose timers (TIM12/13/14) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –... - Page 382 General-purpose timers (TIM12/13/14) RM0041 Output compare mode Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. 000: Frozen.
- Page 383 RM0041 General-purpose timers (TIM12/13/14) Input capture mode Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1.
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Page 384: Tim13/14 Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM12/13/14) RM0041 14.5.6 TIM13/14 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 CC1NP CC1P CC1E Reserved Res. Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared. CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description). -
Page 385: Tim13/14 Counter (Timx_Cnt)
RM0041 General-purpose timers (TIM12/13/14) 14.5.7 TIM13/14 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 14.5.8 TIM13/14 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). -
Page 386: Tim13/14 Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM12/13/14) RM0041 14.5.10 TIM13/14 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). -
Page 387: Tim13/14 Register Map
RM0041 General-purpose timers (TIM12/13/14) 14.5.11 TIM13/14 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below. Table 78. TIM13/14 register map and reset values Offset Register TIMx_CR1 Reserve [1:0] 0x00 Reserved Reset value TIMx_SMCR 0x08 Reserved Reset value... -
Page 388: General-Purpose Timers (Tim15/16/17)
General-purpose timers (TIM15/16/17) RM0041 General-purpose timers (TIM15/16/17) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 389: Tim15 Main Features
RM0041 General-purpose timers (TIM15/16/17) 15.2 TIM15 main features TIM15 includes the following features: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divid (also “on the fly”) the counter clock frequency by any factor between 1 and 65536 • Up to 2 independent channels for: –... -
Page 390: Tim16 And Tim17 Main Features
General-purpose timers (TIM15/16/17) RM0041 15.3 TIM16 and TIM17 main features The TIM16 and TIM17 timers include the following features: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536 •... -
Page 391: Figure 157. Tim15 Block Diagram
RM0041 General-purpose timers (TIM15/16/17) Figure 157. TIM15 block diagram Internal clock (CK_INT) CK_TIM1121314151617 from RCC Trigger controller TRGO to other timers ITR0 ITR1 Slave Reset, enable, up, count ITR2 mode TRGI controller ITR3 TI1F_ED TI1FP1 TI2FP2 REP register Auto-reload register Repetition counter Stop, clear... -
Page 392: Figure 158. Tim16 And Tim17 Block Diagram
General-purpose timers (TIM15/16/17) RM0041 Figure 158. TIM16 and TIM17 block diagram Internal clock (CK_INT) Counter Enable (CEN) REP register Auto-reload register Repetition Stop, clear or up/down counter CK_PSC CK_CNT CNT counter prescaler DTG registers CC1I TIMx_CH1 TI1FP1 Input filter & IC1PS OC1REF TIMx_CH1... -
Page 393: Tim15/16/17 Functional Description
RM0041 General-purpose timers (TIM15/16/17) 15.4 TIM15/16/17 functional description 15.4.1 Time-base unit The main block of the programmable timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler. -
Page 394: Counter Modes
General-purpose timers (TIM15/16/17) RM0041 Figure 159. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 160. -
Page 395: Figure 161. Counter Timing Diagram, Internal Clock Divided By 1
RM0041 General-purpose timers (TIM15/16/17) preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). -
Page 396: Figure 163. Counter Timing Diagram, Internal Clock Divided By 4
General-purpose timers (TIM15/16/17) RM0041 Figure 163. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 164. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register... -
Page 397: Repetition Counter
RM0041 General-purpose timers (TIM15/16/17) Figure 166. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register Write a new value in TIMx_ARR... -
Page 398: Clock Selection
General-purpose timers (TIM15/16/17) RM0041 Figure 167. Update rate examples depending on mode and TIMx_RCR register settings Edge-aligned mode Upcounting Counter TIMx_CNT TIMx_RCR = 0 TIMx_RCR = 1 TIMx_RCR = 2 TIMx_RCR = 3 TIMx_RCR re-synchronization (by SW) Update Event: Preload registers transferred to active registers and update interrupt generated ai17332 15.4.4 Clock selection... -
Page 399: Figure 168. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0041 General-purpose timers (TIM15/16/17) Figure 168. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 32 33 34 35 36 01 02 03 04 05 06 07 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. -
Page 400: Capture/Compare Channels
General-purpose timers (TIM15/16/17) RM0041 Figure 170. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 15.4.5 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). -
Page 401: Figure 172. Capture/Compare Channel 1 Main Circuit
RM0041 General-purpose timers (TIM15/16/17) Figure 172. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H write_in_progress read CCR1H read_in_progress write CCR1L Capture/compare preload register read CCR1L CC1S[1] output compare_transfer capture_transfer mode CC1S[0] input CC1S[1] OC1PE mode OC1PE Capture/compare shadow register CC1S[0] TIM1_CCMR1 (from time... -
Page 402: Input Capture Mode
General-purpose timers (TIM15/16/17) RM0041 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. -
Page 403: Pwm Input Mode (Only For Tim15)
RM0041 General-purpose timers (TIM15/16/17) Note: IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. 15.4.7 PWM input mode (only for TIM15) This mode is a particular case of input capture mode. The procedure is the same except: •... -
Page 404: Forced Output Mode
General-purpose timers (TIM15/16/17) RM0041 15.4.8 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, user just needs to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. -
Page 405: Pwm Mode
RM0041 General-purpose timers (TIM15/16/17) Select the counter clock (internal, external, prescaler). Write the desired data in the TIMx_ARR and TIMx_CCRx registers. Set the CCxIE bit if an interrupt request is to be generated. Select the output mode. For example: – Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx –... -
Page 406: Figure 177. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM15/16/17) RM0041 OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details. -
Page 407: Complementary Outputs And Dead-Time Insertion
RM0041 General-purpose timers (TIM15/16/17) 15.4.11 Complementary outputs and dead-time insertion The TIM15/16/17 general-purpose timers can output one complementary signal and manage the switching-off and switching-on of the outputs. This time is generally known as dead-time and must be adjusted depending on the devices connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays due to power switches...) The polarity of the outputs (main output OCx or complementary OCxN) can be selected... -
Page 408: Using The Break Function
General-purpose timers (TIM15/16/17) RM0041 Figure 180. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 15.5.15: TIM15 break and dead-time register (TIM15_BDTR) on page 431 for delay calculation. - Page 409 RM0041 General-purpose timers (TIM15/16/17) delay (dummy instruction) must be inserted before reading it correctly. This is because user writes the asynchronous signal and reads the synchronous signal. When a break occurs (selected level on the break input): • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the OSSI bit).
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Page 410: Figure 181. Output Behavior In Response To A Break
General-purpose timers (TIM15/16/17) RM0041 Figure 181. Output behavior in response to a break. BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay... -
Page 411: One-Pulse Mode
RM0041 General-purpose timers (TIM15/16/17) 15.4.13 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. - Page 412 General-purpose timers (TIM15/16/17) RM0041 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
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Page 413: Tim15 And External Trigger Synchronization (Only For Tim15)
RM0041 General-purpose timers (TIM15/16/17) 15.4.14 TIM15 and external trigger synchronization (only for TIM15) The TIM15 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. -
Page 414: Figure 184. Control Circuit In Gated Mode
General-purpose timers (TIM15/16/17) RM0041 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). -
Page 415: Timer Synchronization
RM0041 General-purpose timers (TIM15/16/17) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). -
Page 416: Tim15 Control Register 1 (Tim15_Cr1)
General-purpose timers (TIM15/16/17) RM0041 15.5.1 TIM15 control register 1 (TIM15_CR1) Address offset: 0x00 Reset value: 0x0000 CKD[1:0] ARPE UDIS Reserved Reserved Bits 15:10 Reserved, must be kept at reset value. Bits 9:8 CKD[1:0]: Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t ) used by the dead-time generators and the digital filters (TIx) -
Page 417: Tim15 Control Register 2 (Tim15_Cr2)
RM0041 General-purpose timers (TIM15/16/17) 15.5.2 TIM15 control register 2 (TIM15_CR2) Address offset: 0x04 Reset value: 0x0000 OIS2 OIS1N OIS1 MMS[2:0] CCDS CCUS CCPC Reserved Res. Res. Bit 15:11 Reserved, must be kept at reset value. Bit 10 OIS2: Output idle state 2 (OC2 output) 0: OC2=0 when MOE=0 1: OC2=1 when MOE=0 Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed... -
Page 418: Tim15 Slave Mode Control Register (Tim15_Smcr)
General-purpose timers (TIM15/16/17) RM0041 Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. -
Page 419: Table 79. Timx Internal Trigger Connection
RM0041 General-purpose timers (TIM15/16/17) Bits 6:4 TS[2:0]: Trigger selection This bitfield selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) -
Page 420: Tim15 Dma/Interrupt Enable Register (Tim15_Dier)
General-purpose timers (TIM15/16/17) RM0041 15.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER) Address offset: 0x0C Reset value: 0x0000 CC2DE CC1DE COMIE CC2IE CC1IE Res. Reserved Reserved Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bits 13:11... -
Page 421: Tim15 Status Register (Tim15_Sr)
RM0041 General-purpose timers (TIM15/16/17) 15.5.5 TIM15 status register (TIM15_SR) Address offset: 0x10 Reset value: 0x0000 CC2OF CC1OF COMIF CC2IF CC1IF Reserved Res. Reserved rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/Compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input... -
Page 422: Tim15 Event Generation Register (Tim15_Egr)
General-purpose timers (TIM15/16/17) RM0041 Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). -
Page 423: Tim15 Capture/Compare Mode Register 1 (Tim15_Ccmr1)
RM0041 General-purpose timers (TIM15/16/17) Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output. - Page 424 General-purpose timers (TIM15/16/17) RM0041 Output compare mode: Bit 15 Reserved, must be kept at reset value. Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input.
- Page 425 RM0041 General-purpose timers (TIM15/16/17) Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
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Page 426: Tim15 Capture/Compare Enable Register (Tim15_Ccer)
General-purpose timers (TIM15/16/17) RM0041 Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f... - Page 427 RM0041 General-purpose timers (TIM15/16/17) Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity 0: OC1N active high 1: OC1N active low Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00”...
- Page 428 General-purpose timers (TIM15/16/17) RM0041 Table 80. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSR MOE bit OSSI bit CCxE bit CCxNE bit OCx output state OCxN output state Output Disabled (not Output Disabled (not driven by driven by the timer) the timer)
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Page 429: Tim15 Counter (Tim15_Cnt)
RM0041 General-purpose timers (TIM15/16/17) 15.5.9 TIM15 counter (TIM15_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 15.5.10 TIM15 prescaler (TIM15_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1). -
Page 430: Tim15 Repetition Counter Register (Tim15_Rcr)
General-purpose timers (TIM15/16/17) RM0041 15.5.12 TIM15 repetition counter register (TIM15_RCR) Address offset: 0x30 Reset value: 0x0000 REP[7:0] Reserved Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. -
Page 431: Tim15 Capture/Compare Register 2 (Tim15_Ccr2)
RM0041 General-purpose timers (TIM15/16/17) 15.5.14 TIM15 capture/compare register 2 (TIM15_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). - Page 432 General-purpose timers (TIM15/16/17) RM0041 Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
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Page 433: Tim15 Dma Control Register (Tim15_Dcr)
RM0041 General-purpose timers (TIM15/16/17) Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 15.5.8: TIM15 capture/compare enable register (TIM15_CCER) on page 426). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. -
Page 434: Tim15 Dma Address For Full Transfer (Tim15_Dmar)
General-purpose timers (TIM15/16/17) RM0041 Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers,... -
Page 435: Table 81. Tim15 Register Map And Reset Values
RM0041 General-purpose timers (TIM15/16/17) Table 81. TIM15 register map and reset values Offset Register TIM15_CR1 [1:0] 0x00 Reserved Reserved Reset value TIM15_CR2 MMS[2:0] 0x04 Reserved Reset value TIM15_SMCR TS[2:0] SMS[2:0] 0x08 Reserved Reset value TIM15_DIER 0x0C Reserved Reset value TIM15_SR 0x10 Reserved Reset value... - Page 436 General-purpose timers (TIM15/16/17) RM0041 Table 81. TIM15 register map and reset values (continued) Offset Register TIM15_RCR REP[7:0] 0x30 Reserved Reset value TIM15_CCR1 CCR1[15:0] 0x34 Reserved Reset value TIM15_CCR2 CCR2[15:0] 0x38 Reserved Reset value LOCK TIM15_BDTR DT[7:0] [1:0] 0x44 Reserved Reset value TIM15_DCR DBL[4:0] DBA[4:0]...
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Page 437: Tim16&Tim17 Registers
RM0041 General-purpose timers (TIM15/16/17) 15.6 TIM16&TIM17 registers Refer toSection 1.1: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). -
Page 438: Tim16&Tim17 Control Register 2 (Timx_Cr2)
General-purpose timers (TIM15/16/17) RM0041 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –... - Page 439 RM0041 General-purpose timers (TIM15/16/17) Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
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Page 440: Tim16&Tim17 Dma/Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM15/16/17) RM0041 15.6.3 TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 CC1DE COMIE CC1IE Res. Reserved Reserved Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bist 13:10 Reserved, must be kept at reset value. -
Page 441: Tim16&Tim17 Status Register (Timx_Sr)
RM0041 General-purpose timers (TIM15/16/17) 15.6.4 TIM16&TIM17 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC1OF COMIF CC1IF Reserved Res. Reserved rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. -
Page 442: Tim16&Tim17 Event Generation Register (Timx_Egr)
General-purpose timers (TIM15/16/17) RM0041 Bits 4:2 Reserved, must be kept at reset value. Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). -
Page 443: Tim16&Tim17 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0041 General-purpose timers (TIM15/16/17) Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output. - Page 444 General-purpose timers (TIM15/16/17) RM0041 Output compare mode: Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
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Page 445: Tim16&Tim17 Capture/Compare Enable Register (Timx_Ccer)
RM0041 General-purpose timers (TIM15/16/17) Input capture mode Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. - Page 446 General-purpose timers (TIM15/16/17) RM0041 Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output polarity 0: OC1N active high 1: OC1N active low Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00”...
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Page 447: Table 82. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
RM0041 General-purpose timers (TIM15/16/17) Table 82. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not Output Disabled (not driven by driven by the timer) the timer) OCx=0, OCx_EN=0... -
Page 448: Tim16&Tim17 Counter (Timx_Cnt)
General-purpose timers (TIM15/16/17) RM0041 15.6.8 TIM16&TIM17 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 15.6.9 TIM16&TIM17 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1). -
Page 449: Tim16&Tim17 Repetition Counter Register (Timx_Rcr)
RM0041 General-purpose timers (TIM15/16/17) 15.6.11 TIM16&TIM17 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 REP[7:0] Reserved Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. -
Page 450: Tim16&Tim17 Break And Dead-Time Register (Timx_Bdtr)
General-purpose timers (TIM15/16/17) RM0041 15.6.13 TIM16&TIM17 break and dead-time register (TIMx_BDTR) Address offset: 0x44 Reset value: 0x0000 OSSR OSSI LOCK[1:0] DTG[7:0] Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. -
Page 451: Tim16&Tim17 Dma Control Register (Timx_Dcr)
RM0041 General-purpose timers (TIM15/16/17) Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 15.5.8: TIM15 capture/compare enable register (TIM15_CCER) on page 426). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. -
Page 452: Tim16&Tim17 Dma Address For Full Transfer (Timx_Dmar)
General-purpose timers (TIM15/16/17) RM0041 Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. - Page 453 RM0041 General-purpose timers (TIM15/16/17) Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. –...
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Page 454: Tim16&Tim17 Register Map
General-purpose timers (TIM15/16/17) RM0041 15.6.16 TIM16&TIM17 register map TIM16&TIM17 registers are mapped as 16-bit addressable registers as described in the table below: Table 83. TIM16&TIM17 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reserved Reserved Reset value TIMx_CR2 MMS[2:0] 0x04 Reserved... - Page 455 RM0041 General-purpose timers (TIM15/16/17) Table 83. TIM16&TIM17 register map and reset values (continued) Offset Register TIMx_RCR REP[7:0] 0x30 Reserved Reset value TIMx_CCR1 CCR1[15:0] 0x34 Reserved Reset value LOCK TIMx_BDTR DT[7:0] [1:0] 0x44 Reserved Reset value TIMx_DCR DBL[4:0] DBA[4:0] Reserve 0x48 Reserved Reset value TIMx_DMAR...
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Page 456: Basic Timers (Tim6 And Tim7)
Basic timers (TIM6 and TIM7) RM0041 Basic timers (TIM6 and TIM7) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 457: Tim6 And Tim7 Functional Description
RM0041 Basic timers (TIM6 and TIM7) Figure 186. Basic timer block diagram TRGO Trigger Internal clock (CK_INT) to DAC TIMxCLK from RCC controller Reset, Enable, Count, Controller Auto-reload Register Stop, Clear or up CK_PSC CK_CNT ± Prescaler COUNTER Flag Preload registers transferred to active registers on U event according to control bit event interrupt &... -
Page 458: Figure 187. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timers (TIM6 and TIM7) RM0041 Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event. -
Page 459: Counting Mode
RM0041 Basic timers (TIM6 and TIM7) Figure 188. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register FA FB Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31077V3... -
Page 460: Figure 189. Counter Timing Diagram, Internal Clock Divided By 1
Basic timers (TIM6 and TIM7) RM0041 Figure 189. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timerclock = CK_CNT Counter register 34 35 36 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS37364V1 Figure 190. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timerclock = CK_CNT... -
Page 461: Figure 191. Counter Timing Diagram, Internal Clock Divided By 4
RM0041 Basic timers (TIM6 and TIM7) Figure 191. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN Timerclock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) MSv37301V1 Figure 192. Counter timing diagram, internal clock divided by N CK_INT Timerclock = CK_CNT Counter register... -
Page 462: Clock Source
Basic timers (TIM6 and TIM7) RM0041 Figure 194. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register... -
Page 463: Debug Mode
RM0041 Basic timers (TIM6 and TIM7) 16.3.4 Debug mode ® When the microcontroller enters the debug mode (Cortex -M3 core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 25.15.2: Debug support for timers, watchdog and I 16.4... - Page 464 Basic timers (TIM6 and TIM7) RM0041 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: –...
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Page 465: Tim6 And Tim7 Control Register 2 (Timx_Cr2)
RM0041 Basic timers (TIM6 and TIM7) 16.4.2 TIM6 and TIM7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 MMS[2:0] Reserved Reserved Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS[2:0]: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). -
Page 466: Tim6 And Tim7 Status Register (Timx_Sr)
Basic timers (TIM6 and TIM7) RM0041 16.4.4 TIM6 and TIM7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Reserved rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. -
Page 467: Tim6 And Tim7 Prescaler (Timx_Psc)
RM0041 Basic timers (TIM6 and TIM7) 16.4.7 TIM6 and TIM7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). -
Page 468: Tim6 And Tim7 Register Map
Basic timers (TIM6 and TIM7) RM0041 16.4.9 TIM6 and TIM7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below. Table 84. TIM6 and TIM7 register map and reset values Offset Register TIMx_CR1 0x00 Reserved Reset value TIMx_CR2... -
Page 469: Real-Time Clock (Rtc)
RM0041 Real-time clock (RTC) Real-time clock (RTC) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 470: Rtc Main Features
Real-time clock (RTC) RM0041 17.2 RTC main features • Programmable prescaler: division factor up to 2 • 32-bit programmable counter for long-term measurement • Two separate clocks: PCLK1 for the APB1 interface and RTC clock (must be at least four times slower than the PCLK1 clock) •... -
Page 471: Rtc Functional Description
RM0041 Real-time clock (RTC) 17.3 RTC functional description 17.3.1 Overview The RTC consists of two main units (see Figure 196). The first one (APB1 Interface) is used to interface with the APB1 bus. This unit also contains a set of 16-bit registers accessible from the APB1 bus in read or write mode (for more information refer to Section 17.4: RTC registers). -
Page 472: Resetting Rtc Registers
Real-time clock (RTC) RM0041 17.3.2 Resetting RTC registers All system registers are asynchronously reset by a System Reset or Power Reset, except for RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV. The RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup Domain reset. -
Page 473: Rtc Flag Assertion
RM0041 Real-time clock (RTC) 17.3.5 RTC flag assertion The RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update of the RTC Counter. The RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the counter reaches 0x0000. -
Page 474: Rtc Registers
Real-time clock (RTC) RM0041 17.4 RTC registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 17.4.1 RTC control register high (RTC_CRH) Address offset: 0x00 Reset value: 0x0000 OWIE... -
Page 475: Rtc Control Register Low (Rtc_Crl)
RM0041 Real-time clock (RTC) 17.4.2 RTC control register low (RTC_CRL) Address offset: 0x04 Reset value: 0x0020 RTOFF ALRF SECF Reserved rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:6 Reserved, forced by hardware to 0. Bit 5 RTOFF: RTC operation OFF With this bit the RTC reports the status of the last write operation performed on its registers, indicating if it has been completed or not. -
Page 476: Rtc Prescaler Load Register (Rtc_Prlh / Rtc_Prll)
Real-time clock (RTC) RM0041 The functions of the RTC are controlled by this control register. It is not possible to write to the RTC_CR register while the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 17.3.4: Configuring RTC registers). -
Page 477: Rtc Prescaler Divider Register (Rtc_Divh / Rtc_Divl)
RM0041 Real-time clock (RTC) RTC prescaler load register low (RTC_PRLL) Address offset: 0x0C Write only (see Section 17.3.4: Configuring RTC registers) Reset value: 0x8000 PRL[15:0] Bits 15:0 PRL[15:0]: RTC prescaler reload value low These bits are used to define the counter clock frequency according to the following formula: /(PRL[19:0]+1) TR_CLK RTCCLK... -
Page 478: Rtc Counter Register (Rtc_Cnth / Rtc_Cntl)
Real-time clock (RTC) RM0041 17.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) The RTC core has one 32-bit programmable counter, accessed through two 16-bit registers; the count rate is based on the TR_CLK time reference, generated by the prescaler. RTC_CNT registers keep the counting value of this counter. They are write-protected by bit RTOFF in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. -
Page 479: Rtc Alarm Register High (Rtc_Alrh / Rtc_Alrl)
RM0041 Real-time clock (RTC) 17.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) When the programmable counter reaches the 32-bit value stored in the RTC_ALR register, an alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. -
Page 480: Rtc Register Map
Real-time clock (RTC) RM0041 17.4.7 RTC register map RTC registers are mapped as 16-bit addressable registers as described in the table below: Table 85. register map and reset values Offset Register RTC_CRH 0x00 Reserved 0 0 0 Reset value RTC_CRL 0x04 Reserved 1 0 0 0 0 0... -
Page 481: Independent Watchdog (Iwdg)
RM0041 Independent watchdog (IWDG) Independent watchdog (IWDG) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 482: Hardware Watchdog
Independent watchdog (IWDG) RM0041 18.3.1 Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the Key register is written by the software before the counter reaches end of count. 18.3.2 Register access protection Write access to the IWDG_PR and IWDG_RLR registers is protected. -
Page 483: Iwdg Registers
RM0041 Independent watchdog (IWDG) 1. These timings are given for a kHz clock but the microcontroller internal RC frequency can vary. Refer to the LSI oscillator characteristics table in the device datasheet for maximum and minimum values. The LSI can be calibrated so as to compute the IWDG timeout with an acceptable accuracy. For more details refer to Section 7.2.5: LSI clock. -
Page 484: Reload Register (Iwdg_Rlr)
Independent watchdog (IWDG) RM0041 Bits 31:3 Reserved, must be kept at reset value. Bits 2:0 PR[2:0]: Prescaler divider These bits are write access protected seeSection 18.3.2. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. - Page 485 RM0041 Independent watchdog (IWDG) Bits 31:2 Reserved, must be kept at reset value. Bit 1 RVU: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the V voltage domain (takes up to 5 RC 40 kHz cycles).
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Page 486: Iwdg Register Map
Independent watchdog (IWDG) RM0041 18.4.5 IWDG register map The following table gives the IWDG register map and reset values. Table 87. IWDG register map and reset values Offset Register IWDG_KR KEY[15:0] Reserved 0x00 Reset value IWDG_PR PR[2:0] Reserved 0x04 Reset value IWDG_RLR RL[11:0] Reserved... -
Page 487: Window Watchdog (Wwdg)
RM0041 Window watchdog (WWDG) Window watchdog (WWDG) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 488: Figure 200. Watchdog Block Diagram
Window watchdog (WWDG) RM0041 Figure 200. Watchdog block diagram The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0. -
Page 489: How To Program The Watchdog Timeout
RM0041 Window watchdog (WWDG) In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions. -
Page 490: Debug Mode
Window watchdog (WWDG) RM0041 As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63: ⁄ × × × t WWDG 24000 4096 87.38ms Refer to Table 88 for the minimum and maximum values of the t WWDG Table 88. -
Page 491: Wwdg Registers
RM0041 Window watchdog (WWDG) 19.6 WWDG registers Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 19.6.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F Reserved... -
Page 492: Configuration Register (Wwdg_Cfr)
Window watchdog (WWDG) RM0041 19.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F Reserved WDGTB[1:0] W[6:0] Reserved Bit 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. -
Page 493: Wwdg Register Map
RM0041 Window watchdog (WWDG) 19.6.4 WWDG register map The following table gives the WWDG register map and reset values. Table 89. WWDG register map and reset values Offset Register WWDG_CR T[6:0] 0x00 Reserved Reset value WWDG_CFR W[6:0] 0x04 Reserved Reset value WWDG_SR 0x08 Reserved... -
Page 494: Flexible Static Memory Controller (Fsmc)
Flexible static memory controller (FSMC) RM0041 Flexible static memory controller (FSMC) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 495: Block Diagram
RM0041 Flexible static memory controller (FSMC) operation is in progress, the FIFO is drained. The FSMC inserts wait states until the current memory access is complete. • External asynchronous wait control The FSMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. -
Page 496: Supported Memories And Transactions
Flexible static memory controller (FSMC) RM0041 The FSMC generates an AHB error in the following conditions: • When reading or writing to an FSMC bank which is not enabled • When reading or writing to the NOR flash bank while the FACCEN bit is reset in the FSMC_BCRx register. -
Page 497: External Device Address Mapping
RM0041 Flexible static memory controller (FSMC) 20.4 External device address mapping From the FSMC point of view, the external memory is composed of a single fixed size bank of 256 Mbytes (Refer to Figure 203): • Bank 1 used to address up to four NOR flash or PSRAM memory devices. This bank is split into 4 NOR/PSRAM subbanks with four dedicated chip selects, as follows: –... -
Page 498: Nor Flash/Psram Controller
Flexible static memory controller (FSMC) RM0041 1. In case of a 16-bit external memory width, the FSMC internally uses HADDR[25:1] to generate the address for external memory FSMC_A[24:0]. Whatever the external memory width (16-bit or 8-bit), FSMC_A[0] should be connected to external memory address A[0]. -
Page 499: External Memory Interface Signals
RM0041 Flexible static memory controller (FSMC) Table 92. Programmable NOR/PSRAM access parameters (continued) Parameter Function Access mode Unit Min. Max. Number of AHB clock cycles Clock divide AHB clock cycle (HCLK) to build one memory Synchronous ratio (HCLK) clock cycle (CLK) Number of clock cycles to Memory clock Data latency... -
Page 500: Table 95. Nonmultiplexed I/Os Psram/Sram
Flexible static memory controller (FSMC) RM0041 Table 94. Multiplexed I/O NOR flash (continued) FSMC signal name Function Latch enable (this signal is called address valid, NADV, by some NOR NL(=NADV) flash devices) NWAIT NOR flash wait input signal to the FSMC NOR-flash memories are addressed in 16-bit words. -
Page 501: Supported Memories And Transactions
RM0041 Flexible static memory controller (FSMC) Table 96. Multiplexed I/O PSRAM (continued) FSMC signal name Function NBL[1] Upper byte enable (memory signal name: NUB) NBL[0] Lowed byte enable (memory signal name: NLB) PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines). -
Page 502: General Timing Rules
Flexible static memory controller (FSMC) RM0041 Table 97. NOR flash/PSRAM controller: example of supported memories and transactions Allowed/ Memory Device Mode data Comments data size size allowed Asynchronous 8 / 16 Asynchronous 8 / 16 Use of byte lanes NBL[1:0] SRAM and ROM Asynchronous Split into two FSMC accesses... -
Page 503: Figure 204. Mode1 Read Accesses
RM0041 Flexible static memory controller (FSMC) Figure 204. Mode1 read accesses Memory transaction A[25:0] NBL[1:0] High data driven D[15:0] by memory ADDSET DATAST HCLK cycles HCLK cycles ai15557 1. NBL[1:0] are driven low during read access. Figure 205. Mode1 write accesses Memory transaction A[25:0] NBL[1:0]... -
Page 504: Table 98. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0041 Table 98. FSMC_BCRx bit fields Bit number Bit name Value to set 31-20 Reserved 0x000 CBURSTRW 0x0 (no effect on asynchronous mode) 18:16 CPSIZE 0x0 (no effect on asynchronous mode) ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0. EXTMOD WAITEN 0x0 (no effect on asynchronous mode) -
Page 505: Figure 206. Modea Read Accesses
RM0041 Flexible static memory controller (FSMC) Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 206. ModeA read accesses Memory transaction A[25:0] NBL[1:0] High data driven D[15:0] by memory ADDSET DATAST HCLK cycles HCLK cycles ai15559 1. NBL[1:0] are driven low during read access. Figure 207. -
Page 506: Table 100. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0041 The differences compared with mode1 are the toggling of NOE and the independent read and write timings. Table 100. FSMC_BCRx bit fields Bit name Value to set number 31-20 Reserved 0x000 CBURSTRW 0x0 (no effect on asynchronous mode) 18:16 CPSIZE 0x0 (no effect on asynchronous mode) -
Page 507: Table 102. Fsmc_Bwtrx Bit Fields
RM0041 Flexible static memory controller (FSMC) Table 102. FSMC_BWTRx bit fields Bit name Value to set number 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+1 HCLK cycles for 15-8 DATAST... -
Page 508: Figure 209. Mode2 Write Accesses
Flexible static memory controller (FSMC) RM0041 Figure 209. Mode2 write accesses Memory transaction A[25:0] NADV 1HCLK D[15:0] data driven by FSMC ADDSET (DATAST + 1) HCLK cycles HCLK cycles ai15562 Figure 210. Mode B write accesses Memory transaction A[25:0] NADV 1HCLK D[15:0] data driven by FSMC... -
Page 509: Table 103. Fsmc_Bcrx Bit Fields
RM0041 Flexible static memory controller (FSMC) Table 103. FSMC_BCRx bit fields Bit name Value to set number 31-20 Reserved 0x000 CBURSTRW 0x0 (no effect on asynchronous mode) 18:16 Reserved 0x0 (no effect on asynchronous mode) Set to 1 if the memory supports this feature. Otherwise keep at ASYNCWAIT EXTMOD 0x1 for mode B, 0x0 for mode 2... -
Page 510: Table 105. Fsmc_Bwtrx Bit Fields
Flexible static memory controller (FSMC) RM0041 Table 105. FSMC_BWTRx bit fields Bit name Value to set number 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+1 HCLK cycles for 15-8 DATAST... -
Page 511: Table 106. Fsmc_Bcrx Bit Fields
RM0041 Flexible static memory controller (FSMC) Figure 212. Mode C write accesses Memory transaction A[25:0] NADV 1HCLK D[15:0] data driven by FSMC ADDSET (DATAST + 1) HCLK cycles HCLK cycles ai15565 The differences compared with mode1 are the toggling of NOE and the independent read and write timings. -
Page 512: Table 107. Fsmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0041 Table 106. FSMC_BCRx bit fields (continued) Bit No. Bit name Value to set MUXEN MBKEN Table 107. FSMC_BTRx bit fields Bit name Value to set number 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT 23-20 CLKDIV 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) -
Page 513: Figure 213. Mode D Read Accesses
RM0041 Flexible static memory controller (FSMC) Mode D - asynchronous access with extended address Figure 213. Mode D read accesses Memory transaction A[25:0] NADV High data driven D[15:0] by memory ADDSET DATAST HCLK cycles HCLK cycles ADDHLD HCLK cycles ai15566 Figure 214. -
Page 514: Table 109. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0041 The differences with mode1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings. Table 109. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-20 Reserved 0x000... -
Page 515: Table 111. Fsmc_Bwtrx Bit Fields
RM0041 Flexible static memory controller (FSMC) Table 111. FSMC_BWTRx bit fields Bit No. Bit name Value to set 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT 23-20 CLKDIV 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) 15-8 DATAST Duration of the second access phase Duration of the middle phase of the write access (ADDHLD HCLK ADDHLD cycles) -
Page 516: Table 112. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0041 Figure 216. Multiplexed write accesses Memory transaction A[25:16] NADV 1HCLK AD[15:0] Lower address data driven by FSMC ADDSET ADDHLD (DATAST + 1) HCLK cycles HCLK cycles HCLK cycles ai15569 The difference with mode D is the drive of the lower address byte(s) on the databus. Table 112. -
Page 517: Table 113. Fsmc_Btrx Bit Fields
RM0041 Flexible static memory controller (FSMC) Table 112. FSMC_BCRx bit fields (continued) Bit No. Bit name Value to set MUXEN MBKEN Table 113. FSMC_BTRx bit fields Bit No. Bit name Value to set 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care... -
Page 518: Figure 217. Asynchronous Wait During A Read Access
Flexible static memory controller (FSMC) RM0041 DATAST in FSMC_BTRx register) Memory asserts the WAIT signal aligned to NOE/NWE which toggles: ≥ × DATAST HCLK max_wait_assertion_time Memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): > max_wait_assertion_time address_phase hold_phase then –... -
Page 519: Figure 218. Asynchronous Wait During A Write Access
RM0041 Flexible static memory controller (FSMC) Figure 218. Asynchronous wait during a write access Memory transaction A[25:0] address phase data setup phase NWAIT don’t care don’t care 1HCLK D[15:0] data driven by FSMC 3HCLK ai15797c 1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register. RM0041 Rev 6 519/709... -
Page 520: Synchronous Transactions
Flexible static memory controller (FSMC) RM0041 20.5.5 Synchronous transactions The memory clock, CLK, is a submultiple of HCLK according to the value of parameter CLKDIV. NOR flash memories specify a minimum time from NADV assertion to CLK high. To meet this constraint, the FSMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion). -
Page 521: Figure 219. Wait Configurations
RM0041 Flexible static memory controller (FSMC) When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) or on the next clock edge (bit WAITCFG = 0). During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid, and does not consider the data valid. -
Page 522: Table 114. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0041 Figure 220. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) Memory transaction = burst of 4 half words HCLK A[25:16] addr[25:16] High NADV NWAIT (WAITCFG= (DATLAT + 2) inserted wait state CLK cycles A/D[15:0] Addr[15:0] data data... -
Page 523: Table 115. Fsmc_Btrx Bit Fields
RM0041 Flexible static memory controller (FSMC) Table 114. FSMC_BCRx bit fields (continued) Bit No. Bit name Value to set MTYP[0:1] 0x1 or 0x2 MUXEN As needed MBKEN Table 115. FSMC_BTRx bit fields Bit No. Bit name Value to set 31:30 Reserved 29:28 ACCMOD... -
Page 524: Table 116. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0041 Figure 221. Synchronous multiplexed write mode - PSRAM (CRAM) Memory transaction = burst of 2 half words HCLK A[25:16] addr[25:16] Hi-Z NADV NWAIT (WAITCFG = 0) (DATLAT + 2) inserted wait state CLK cycles A/D[15:0] Addr[15:0] data... -
Page 525: Table 117. Fsmc_Btrx Bit Fields
RM0041 Flexible static memory controller (FSMC) Table 116. FSMC_BCRx bit fields (continued) Bit No. Bit name Value to set WAITPOL to be set according to memory BURSTEN no effect on synchronous write Reserved FACCEN Set according to memory support MWID As needed MTYP[0:1] MUXEN... -
Page 526: Nor/Psram Control Registers
Flexible static memory controller (FSMC) RM0041 20.5.6 NOR/PSRAM control registers The NOR/PSRAM control registers have to be accessed by words (32 bits). SRAM/NOR-flash chip-select control registers 1..4 (FSMC_BCR1..4) Address offset: 0xA000 0000 + 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR flash memories. - Page 527 RM0041 Flexible static memory controller (FSMC) Bit 14 EXTMOD: Extended mode enable. This bit enables the FSMC to program the write timings for non-multiplexed asynchronous accesses inside the FSMC_BWTR register, thus resulting in different timings for read and write operations. 0: values inside FSMC_BWTR register are not taken into account (default after reset) 1: values inside FSMC_BWTR register are taken into account Note: When the extended mode is disabled, the FSMC can operate in Mode1 or Mode2...
- Page 528 Flexible static memory controller (FSMC) RM0041 Bit 7 Reserved, must be kept at reset value. Bit 6 FACCEN: Flash access enable Enables NOR flash memory access operations. 0: Corresponding NOR flash memory access is disabled 1: Corresponding NOR flash memory access is enabled (default after reset) Bits 5:4 MWID[1:0]: Memory databus width.
- Page 529 RM0041 Flexible static memory controller (FSMC) SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) Address offset: 0xA000 0000 + 0x04 + 8 * (x – 1), x = 1..4 Reset value: 0x0FFF FFFF FSMC_BTRx bits are written by software to add a delay at the end of a read /write transaction.
- Page 530 Flexible static memory controller (FSMC) RM0041 Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read (and read-to write) transaction. The programmed bus turnaround delay is inserted between an asynchronous read (muxed or D mode) or a write transaction and any other asynchronous/synchronous read or write to/from a static bank (for a read operation, the bank can be the same or a different one;...
- Page 531 RM0041 Flexible static memory controller (FSMC) Bits 15:8 DATAST[7:0]: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 204 Figure 216), used in asynchronous accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 1 × HCLK clock cycles 0000 0010: DATAST phase duration = 2 ×...
- Page 532 Flexible static memory controller (FSMC) RM0041 SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) Address offset: 0xA000 0000 + 0x104 + 8 * (x – 1), x = 1...4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, PSRAMs and NOR flash memories.
- Page 533 RM0041 Flexible static memory controller (FSMC) Bits 15:8 DATAST[7:0]: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 204 Figure 216), used in asynchronous SRAM, PSRAM and NOR flash memory accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 1 ×...
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Page 534: Fsmc Register Map
Flexible static memory controller (FSMC) RM0041 20.5.7 FSMC register map The following table summarizes the FSMC registers. Table 118. FSMC register map Offset Register 0000 FSMC_BCR1 Reserved 0008 FSMC_BCR2 Reserved 0010 FSMC_BCR3 Reserved 0018 FSMC_BCR4 Reserved 0004 FSMC_BTR1 Res. ADDSET[3:0] 000C FSMC_BTR2 Res. - Page 535 RM0041 Flexible static memory controller (FSMC) Table 118. FSMC register map (continued) Offset Register FSMC_BWTR 0114 Res. Res. [1:0] FSMC_BWTR 011C Res. Res. [1:0] Refer to for the register boundary addresses. RM0041 Rev 6 535/709...
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Page 536: Serial Peripheral Interface (Spi)
Serial peripheral interface (SPI) RM0041 Serial peripheral interface (SPI) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 537: Spi Main Features
RM0041 Serial peripheral interface (SPI) 21.2 SPI main features 21.2.1 SPI features • Full-duplex synchronous transfers on three lines • Simplex synchronous transfers on two lines with or without a bidirectional data line • 8- or 16-bit transfer frame format selection •... -
Page 538: Spi Functional Description
Serial peripheral interface (SPI) RM0041 21.3 SPI functional description 21.3.1 General description The block diagram of the SPI is shown in Figure 222. Figure 222. SPI block diagram Address and data bus Read Rx buffer SPI_CR2 MOSI RXNE TXDM RXDM SSOE Shift register MISO... -
Page 539: Figure 223. Single Master/ Single Slave Application
RM0041 Serial peripheral interface (SPI) Figure 223. Single master/ single slave application Master Slave MSBit LSBit MSBit LSBit MISO MISO 8-bit shift register 8-bit shift register MOSI MOSI SPI clock generator Not used if NSS is managed by software ai14745 1. - Page 540 Serial peripheral interface (SPI) RM0041 Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the SPI_CR1 register. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred.
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Page 541: Figure 224. Data Clock Timing Diagram
RM0041 Serial peripheral interface (SPI) Figure 224. Data clock timing diagram CPHA =1 CPOL = 1 CPOL = 0 MOSI LSBit MSBit MISO LSBit MSBit (to slave) Capture strobe CPHA =0 CPOL = 1 CPOL = 0 MOSI LSBit MSBit MISO MSBit LSBit... -
Page 542: Configuring The Spi In Slave Mode
Serial peripheral interface (SPI) RM0041 21.3.2 Configuring the SPI in slave mode In the slave configuration, the serial clock is received on the SCK pin from the master device. The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data transfer rate. -
Page 543: Configuring The Spi In Master Mode
RM0041 Serial peripheral interface (SPI) 21.3.3 Configuring the SPI in master mode In the master configuration, the serial clock is generated on the SCK pin. Procedure Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register). Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure... -
Page 544: Data Transmission And Reception Procedures
Serial peripheral interface (SPI) RM0041 1 clock and 1 bidirectional data wire (BIDIMODE = 1) This mode is enabled by setting the BIDIMODE bit in the SPI_CR1 register. In this mode SCK is used for the clock and MOSI in master or MISO in slave mode is used for data communication. - Page 545 RM0041 Serial peripheral interface (SPI) Start sequence in master mode • In full-duplex (BIDIMODE=0 and RXONLY=0) – The sequence begins when data are written into the SPI_DR register (Tx buffer). – The data are then parallel loaded from the Tx buffer into the 8-bit shift register during the first bit transmission and then shifted out serially to the MOSI pin.
- Page 546 Serial peripheral interface (SPI) RM0041 software must have written the data to be sent before the SPI master device initiates the transfer. – No data are received. • In bidirectional mode, when receiving (BIDIMODE=1 and BIDIOE=0) – The sequence begins when the slave device receives the clock signal and the first bit of the data on its MISO pin.
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Page 547: Figure 225. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode
RM0041 Serial peripheral interface (SPI) Figure 225. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers Example in Master mode with CPOL=1, CPHA=1 DATA1 = 0xF1 DATA2 = 0xF2 DATA3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware set by hardware... -
Page 548: Figure 226. Txe/Rxne/Bsy Behavior In Slave / Full-Duplex Mode
Serial peripheral interface (SPI) RM0041 Figure 226. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in case of continuous transfers Example in Slave mode with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware... -
Page 549: Figure 227. Txe/Bsy Behavior In Master Transmit-Only Mode (Bidimode=0 And Rxonly=0)
RM0041 Serial peripheral interface (SPI) Figure 227. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers Example in Master mode with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware... -
Page 550: Figure 229. Rxne Behavior In Receive-Only Mode (Bidirmode=0 And Rxonly=1)
Serial peripheral interface (SPI) RM0041 Set the RXONLY bit in the SPI_CR1 register. Enable the SPI by setting the SPE bit to 1: In master mode, this immediately activates the generation of the SCK clock, and data are serially received until the SPI is disabled (SPE=0). In slave mode, data are received when the SPI master device drives NSS low and generates the SCK clock. -
Page 551: Crc Calculation
RM0041 Serial peripheral interface (SPI) In slave mode, the continuity of the communication is decided by the SPI master device. In any case, even if the communication is continuous, the BSY flag goes low between each transfer for a minimum duration of one SPI clock cycle (see Figure 228). - Page 552 Serial peripheral interface (SPI) RM0041 Program the CPOL, CPHA, LSBFirst, BR, SSM, SSI and MSTR values. Program the polynomial in the SPI_CRCPR register. Enable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This also clears the SPI_RXCRCR and SPI_TXCRCR registers. Enable the SPI by setting the SPE bit in the SPI_CR1 register.
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Page 553: Status Flags
RM0041 Serial peripheral interface (SPI) 21.3.7 Status flags Four status flags are provided for the application to completely monitor the state of the SPI bus. Tx buffer empty flag (TXE) When it is set, this flag indicates that the Tx buffer is empty and the next data to be transmitted can be loaded into the buffer. -
Page 554: Disabling The Spi
Serial peripheral interface (SPI) RM0041 21.3.8 Disabling the SPI When a transfer is terminated, the application can stop the communication by disabling the SPI peripheral. This is done by clearing the SPE bit. For some configurations, disabling the SPI and entering the Halt mode while a transfer is ongoing can cause the current transfer to be corrupted and/or the BSY flag might become unreliable. -
Page 555: Spi Communication Using Dma (Direct Memory Addressing)
RM0041 Serial peripheral interface (SPI) 21.3.9 SPI communication using DMA (direct memory addressing) To operate at its maximum speed, the SPI needs to be fed with the data for transmission and the data received on the Rx buffer should be read to avoid overrun. To facilitate the transfers, the SPI features a DMA capability implementing a simple request/acknowledge protocol. -
Page 556: Figure 231. Transmission Using Dma
Serial peripheral interface (SPI) RM0041 Figure 231. Transmission using DMA Example with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware set by hardware cleared by DMA write... -
Page 557: Error Flags
RM0041 Serial peripheral interface (SPI) DMA capability with CRC When SPI communication is enabled with CRC communication and DMA mode, the transmission and reception of the CRC at the end of communication are automatic that is without using the bit CRCNEXT. After the CRC reception, the CRC must be read in the SPI_DR register to clear the RXNE flag. -
Page 558: Spi Interrupts
Serial peripheral interface (SPI) RM0041 CRC error This flag is used to verify the validity of the value received when the CRCEN bit in the SPI_CR1 register is set. The CRCERR flag in the SPI_SR register is set if the value received in the shift register does not match the receiver SPI_RXCRCR value. -
Page 559: Spi Registers
RM0041 Serial peripheral interface (SPI) 21.4 SPI registers The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 21.4.1 SPI control register 1 (SPI_CR1) Address offset: 0x00 Reset value: 0x0000 BIDI BIDI BR [2:0] MSTR CPOL CPHA MODE... -
Page 560: Spi Control Register 2 (Spi_Cr2)
Serial peripheral interface (SPI) RM0041 Bit 8 SSI: Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the IO value of the NSS pin is ignored. Bit 7 LSBFIRST: Frame format 0: MSB transmitted first 1: LSB transmitted first... -
Page 561: Spi Status Register (Spi_Sr)
RM0041 Serial peripheral interface (SPI) Bits 15:8 Reserved, must be kept at reset value. Bit 7 TXEIE: Tx buffer empty interrupt enable 0: TXE interrupt masked 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. Bit 6 RXNEIE: RX buffer not empty interrupt enable 0: RXNE interrupt masked 1: RXNE interrupt not masked. -
Page 562: Spi Data Register (Spi_Dr)
Serial peripheral interface (SPI) RM0041 Bit 5 MODF: Mode fault 0: No mode fault occurred 1: Mode fault occurred This flag is set by hardware and reset by a software sequence. Refer to Section 21.3.10 on page 557 for the software sequence. Bit 4 CRCERR: CRC error flag 0: CRC value received matches the SPI_RXCRCR value 1: CRC value received does not match the SPI_RXCRCR value... -
Page 563: Spi Crc Polynomial Register (Spi_Crcpr)
RM0041 Serial peripheral interface (SPI) 21.4.5 SPI CRC polynomial register (SPI_CRCPR) Address offset: 0x10 Reset value: 0x0007 CRCPOLY[15:0] Bits 15:0 CRCPOLY[15:0]: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. -
Page 564: Spi Tx Crc Register (Spi_Txcrcr)
Serial peripheral interface (SPI) RM0041 21.4.7 SPI TX CRC register (SPI_TXCRCR) Address offset: 0x18 Reset value: 0x0000 TXCRC[15:0] Bits 15:0 TXCRC[15:0]: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. -
Page 565: Spi Register Map
RM0041 Serial peripheral interface (SPI) 21.4.8 SPI register map The table provides shows the SPI register map and reset values. Table 120. SPI register map and reset values Offset Register SPI_CR1 BR [2:0] 0x00 Reserved Reset value SPI_CR2 0x04 Reserved Reset value SPI_SR 0x08... -
Page 566: Inter-Integrated Circuit (I2C) Interface
Inter-integrated circuit (I2C) interface RM0041 Inter-integrated circuit (I2C) interface Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 567: I 2 C Functional Description
RM0041 Inter-integrated circuit (I2C) interface – Arbitration lost condition for master mode – Acknowledgment failure after address/ data transmission – Detection of misplaced start or stop condition – Overrun/Underrun if clock stretching is disabled • 2 Interrupt vectors: – 1 Interrupt for successful address/ data communication –... -
Page 568: Figure 233. I2C Bus Protocol
Inter-integrated circuit (I2C) interface RM0041 Communication flow In Master mode, the I C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. -
Page 569: I2C Slave Mode
RM0041 Inter-integrated circuit (I2C) interface Figure 234. I C block diagram Data register Data Noise Data shift register control filter PEC calculation Comparator Own address register Dual address register Clock Noise PEC register control filter Clock control Register (CCR) Control registers (CR1&CR2) Control Status registers... -
Page 570: Figure 235. Transfer Sequence Diagram For Slave Transmitter
Inter-integrated circuit (I2C) interface RM0041 Header or address not matched: the interface ignores it and waits for another Start condition. Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set and waits for the 8-bit slave address. Address matched: the interface generates in sequence: •... -
Page 571: I2C Master Mode
RM0041 Inter-integrated circuit (I2C) interface Slave receiver Following the address reception and after clearing ADDR, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: •... - Page 572 Inter-integrated circuit (I2C) interface RM0041 Master mode is selected as soon as the Start condition is generated on the bus with a START bit. The following is the required sequence in master mode. • Program the peripheral input clock in I2C_CR2 register in order to generate correct timings •...
- Page 573 RM0041 Inter-integrated circuit (I2C) interface Slave address transmission Then the slave address is sent to the SDA line via the internal shift register. • In 10-bit addressing mode, sending the header sequence causes the following event: – The ADD10 bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.
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Page 574: Figure 237. Transfer Sequence Diagram For Master Transmitter
Inter-integrated circuit (I2C) interface RM0041 Closing the communication After the last byte is written to the DR register, the STOP bit is set by software to generate a Stop condition (see Figure 237 Transfer sequencing EV8_2). The interface automatically goes back to slave mode (MSL bit cleared). Note: Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set. -
Page 575: Figure 238. Method 1: Transfer Sequence Diagram For Master Receiver
RM0041 Inter-integrated circuit (I2C) interface To generate the nonacknowledge pulse after the last received data byte, the ACK bit must be cleared just after reading the second last data byte (after second last RxNE event). To generate the Stop/Restart condition, software must set the STOP/START bit just after reading the second last data byte (after the second last RxNE event). -
Page 576: Figure 239. Method 2: Transfer Sequence Diagram For Master Receiver When N>2
Inter-integrated circuit (I2C) interface RM0041 Figure 239. Method 2: transfer sequence diagram for master receiver when N>2 7- bit master receiver Address Data1 Data2 DataN-2 DataN-1 DataN EV7_2 10- bit master receiver Header Address Header Data1 Data2 DataN-2 DataN-1 DataN EV7_2 Legend: S = Start, S = Repeated Start, P = Stop, A = Acknowledge, NA = Non-acknowledge,... -
Page 577: Figure 240. Method 2: Transfer Sequence Diagram For Master Receiver When N=2
RM0041 Inter-integrated circuit (I2C) interface The procedure described above is valid for N>2. The cases where a single byte or two bytes are to be received should be handled differently, as described below: • Case of a single byte to be received: –... -
Page 578: Error Conditions
Inter-integrated circuit (I2C) interface RM0041 Figure 241. Method 2: transfer sequence diagram for master receiver when N=1 7- bit master receiver Address Data1 EV6_3 10- bit master receiver Header Address Header Data1 EV6_3 Legend: S = Start, S = Repeated Start, P = Stop, A = Acknowledge, NA = Non-acknowledge, EVx = Event (with interrupt if ITEVFEN = 1) EV5: SB=1, cleared by reading SR1 register followed by writing the DR register. -
Page 579: Sda/Scl Line Control
RM0041 Inter-integrated circuit (I2C) interface Arbitration lost (ARLO) This error occurs when the I C interface detects an arbitration lost condition. In this case • the ARLO bit is set by hardware (and an interrupt is generated if the ITERREN bit is set) •... -
Page 580: Smbus
Inter-integrated circuit (I2C) interface RM0041 22.3.6 SMBus Introduction The System Management Bus (SMBus) is a two-wire interface through which various devices can communicate with each other and with the rest of the system. It is based on I principles of operation. SMBus provides a control bus for system and power management related tasks. - Page 581 RM0041 Inter-integrated circuit (I2C) interface Bus protocols The SMBus specification supports up to nine bus protocols. For more details of these protocols and SMBus address types, refer to SMBus specification version. 2.0. These protocols should be implemented by the user software. Address resolution protocol (ARP) SMBus slave address conflicts can be resolved by dynamically assigning a new unique address to each slave device.
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Page 582: Dma Requests
Inter-integrated circuit (I2C) interface RM0041 SEXT as the cumulative clock low extend time for a slave device. SMBus specifies TLOW: MEXT as the cumulative clock low extend time for a master device. For more details on these timeouts, refer to SMBus specification version 2.0. The status flag Timeout or Tlow Error in I2C_SR1 shows the status of this feature. - Page 583 RM0041 Inter-integrated circuit (I2C) interface Set the I2C_DR register address in the DMA_SxPAR register. The data are moved to this address from the memory after each TxE event. Set the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register in the case of a bouble buffer mode).
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Page 584: Packet Error Checking
Inter-integrated circuit (I2C) interface RM0041 22.3.8 Packet error checking A PEC calculator has been implemented to improve the reliability of communication. The PEC is calculated by using the C(x) = x + x + 1 CRC-8 polynomial serially on each bit. •... -
Page 585: Figure 242. I2C Interrupt Mapping Diagram
RM0041 Inter-integrated circuit (I2C) interface Table 122. I C Interrupt requests (continued) Interrupt event Event flag Enable control bit Bus error BERR Arbitration loss (Master) ARLO Acknowledge failure Overrun/Underrun ITERREN PEC error PECERR Timeout/Tlow error TIMEOUT SMBus Alert SMBALERT Note: SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically OR-ed on the same interrupt channel. -
Page 586: I 2 C Debug Mode
Inter-integrated circuit (I2C) interface RM0041 22.5 C debug mode ® When the microcontroller enters the debug mode (Cortex -M3 core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, refer to Section 25.15.2: Debug support for timers, watchdog and I 22.6... - Page 587 RM0041 Inter-integrated circuit (I2C) interface Bit 11 POS: Acknowledge/PEC Position (for data reception) This bit is set and cleared by software and cleared by hardware when PE=0. 0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The PEC bit indicates that current byte in shift register is a PEC.
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Page 588: I 2 C Control Register 2 (I2C_Cr2)
Inter-integrated circuit (I2C) interface RM0041 Bit 3 SMBTYPE: SMBus type 0: SMBus Device 1: SMBus Host Bit 2 Reserved, must be kept at reset value Bit 1 SMBUS: SMBus mode 0: I C mode 1: SMBus mode Bit 0 PE: Peripheral enable 0: Peripheral disable 1: Peripheral enable Note: If this bit is reset while a communication is on going, the peripheral is disabled at the... - Page 589 RM0041 Inter-integrated circuit (I2C) interface Bit 9 ITEVTEN: Event interrupt enable 0: Event interrupt disabled 1: Event interrupt enabled This interrupt is generated when: – SB = 1 (Master) – ADDR = 1 (Master/Slave) – ADD10= 1 (Master) – STOPF = 1 (Slave) –...
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Page 590: I 2 C Own Address Register 1 (I2C_Oar1)
Inter-integrated circuit (I2C) interface RM0041 22.6.3 C Own address register 1 (I2C_OAR1) Address offset: 0x08 Reset value: 0x0000 ADD[9:8] ADD[7:1] ADD0 MODE Reserved Bit 15 ADDMODE Addressing mode (slave mode) 0: 7-bit slave address (10-bit address not acknowledged) 1: 10-bit slave address (7-bit address not acknowledged) Bit 14 Should always be kept at 1 by software. -
Page 591: C Data Register (I2C_Dr)
RM0041 Inter-integrated circuit (I2C) interface 22.6.5 C Data register (I2C_DR) Address offset: 0x10 Reset value: 0x0000 DR[7:0] Reserved Bits 15:8 Reserved, must be kept at reset value Bits 7:0 DR[7:0] 8-bit data register Byte received or to be transmitted to the bus. –... - Page 592 Inter-integrated circuit (I2C) interface RM0041 Bit 14 TIMEOUT: Timeout or Tlow error 0: No timeout error 1: SCL remained LOW for 25 ms (Timeout) Master cumulative clock low extend time more than 10 ms (Tlow:mext) Slave cumulative clock low extend time more than 25 ms (Tlow:sext) –...
- Page 593 RM0041 Inter-integrated circuit (I2C) interface Bit 7 TxE: Data register empty (transmitters) 0: Data register not empty 1: Data register empty – Set when DR is empty in transmission. TxE is not set during address phase. – Cleared by software writing to the DR register or by hardware after a start or a stop condition or when PE=0.
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Page 594: C Status Register 2 (I2C_Sr2)
Inter-integrated circuit (I2C) interface RM0041 Bit 1 ADDR: Address sent (master mode)/matched (slave mode) This bit is cleared by software reading SR1 register followed reading SR2, or by hardware when PE=0. Address matched (Slave) 0: Address mismatched or not received. 1: Received address matched. -
Page 595: I 2 C Clock Control Register (I2C_Ccr)
RM0041 Inter-integrated circuit (I2C) interface Bit 5 SMBDEFAULT: SMBus device default address (Slave mode) 0: No SMBus Device Default address 1: SMBus Device Default address received when ENARP=1 – Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0. Bit 4 GENCALL: General call address (Slave mode) 0: No General Call 1: General Call Address received when ENGC=1... -
Page 596: I 2 C Trise Register (I2C_Trise)
Inter-integrated circuit (I2C) interface RM0041 Bit 15 F/S: I2C master mode selection 0: Sm mode I2C 1: Fm mode I2C Bit 14 DUTY: Fm mode duty cycle 0: Fm mode t high 1: Fm mode t = 16/9 (see CCR) high Bits 13:12 Reserved, must be kept at reset value Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode) - Page 597 RM0041 Inter-integrated circuit (I2C) interface Bits 15:6 Reserved, must be kept at reset value Bits 5:0 TRISE[5:0]: Maximum rise time in Fm/Sm mode (Master mode) These bits should provide the maximum duration of the SCL feedback loop in master mode. The purpose is to keep a stable SCL frequency whatever the SCL rising edge duration.
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Page 598: I2C Register Map
Inter-integrated circuit (I2C) interface RM0041 22.6.10 C register map The table below provides the I C register map and reset values. Table 123. I C register map and reset values Offset Register I2C_CR1 0x00 Reserved Reset value I2C_CR2 FREQ[5:0] 0x04 Reserved Reset value I2C_OAR1... -
Page 599: Universal Synchronous Asynchronous Receiver
RM0041 Universal synchronous asynchronous receiver transmitter (USART) Universal synchronous asynchronous receiver transmitter (USART) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. -
Page 600: Usart Functional Description
Universal synchronous asynchronous receiver transmitter (USART) RM0041 – The Smartcard interface supports the asynchronous protocol Smartcards as defined in the ISO 7816-3 standards – 0.5, 1.5 stop bits for Smartcard operation • Single-wire half-duplex communication • Configurable multibuffer communication using DMA (direct memory access) –... - Page 601 RM0041 Universal synchronous asynchronous receiver transmitter (USART) pin is at high level. In single-wire and smartcard modes, this I/O is used to transmit and receive the data (at USART level, data are then received on SW_RX). Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: •...
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Page 602: Figure 243. Usart Block Diagram
Universal synchronous asynchronous receiver transmitter (USART) RM0041 Figure 243. USART block diagram PRDATA PWDATA Write Read (Data register) DR (CPU or DMA) (CPU or DMA) Receive data register (RDR) Transmit data register (TDR) IrDA SW_RX Receive Shift Register Transmit Shift Register ENDEC block IRDA_OUT... -
Page 603: Usart Character Description
RM0041 Universal synchronous asynchronous receiver transmitter (USART) 23.3.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 244). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data (The number of “1”... -
Page 604: Transmitter
Universal synchronous asynchronous receiver transmitter (USART) RM0041 23.3.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the CK pin. -
Page 605: Figure 245. Configurable Stop Bits
RM0041 Universal synchronous asynchronous receiver transmitter (USART) Figure 245. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next data frame parity Data frame Next Start start Stop Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse a) 1 Stop Bit Possible... -
Page 606: Figure 246. Tc/Txe Behavior When Transmitting
Universal synchronous asynchronous receiver transmitter (USART) RM0041 When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. -
Page 607: Receiver
RM0041 Universal synchronous asynchronous receiver transmitter (USART) Idle characters Setting the TE bit drives the USART to send an idle frame before the first data frame. 23.3.3 Receiver The USART can receive data words of either 8 or 9 bits depending on the M bit in the USART_CR1 register. - Page 608 Universal synchronous asynchronous receiver transmitter (USART) RM0041 3rd, 5th and 7th bits and sampling on the 8th, 9th and 10th bits). If this condition is not met, the start detection aborts and the receiver returns to the idle state (no flag is set). If, for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the 8th, 9th and 10th bits), 2 out of the 3 bits are found at 0, the start bit is validated but the NE noise flag bit is set.
- Page 609 RM0041 Universal synchronous asynchronous receiver transmitter (USART) Overrun error An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared.
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Page 610: Figure 248. Data Sampling When Oversampling By 16
Universal synchronous asynchronous receiver transmitter (USART) RM0041 Programming the ONEBIT bit in the USART_CR3 register selects the method used to evaluate the logic level. There are two options: • the majority vote of the three samples in the center of the received bit. In this case, when the 3 samples used for the majority vote are not equal, the NF bit is set •... -
Page 611: Table 124. Noise Detection From Sampled Data
RM0041 Universal synchronous asynchronous receiver transmitter (USART) Figure 249. Data sampling when oversampling by 8 RX line sampled values Sample clock (x8) One bit time MSv31153V1 Table 124. Noise detection from sampled data Sampled value NE status Received bit value Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a de-... -
Page 612: Fractional Baud Rate Generation
Universal synchronous asynchronous receiver transmitter (USART) RM0041 Configurable stop bits during reception The number of stop bits to be received can be configured through the control bits of Control Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode. 0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit. - Page 613 RM0041 Universal synchronous asynchronous receiver transmitter (USART) How to derive USARTDIV from USART_BRR register values when OVER8=0 Example 1: If DIV_Mantissa = 0d27 and DIV_Fraction = 0d12 (USART_BRR = 0x1BC), then Mantissa (USARTDIV) = 0d27 Fraction (USARTDIV) = 12/16 = 0d0.75 Therefore USARTDIV = 0d27.75 Example 2: To program USARTDIV = 0d25.62...
- Page 614 Universal synchronous asynchronous receiver transmitter (USART) RM0041 Then, USART_BRR = 0x195 => USARTDIV = 0d25.625 Example 3: To program USARTDIV = 0d50.99 This leads to: DIV_Fraction = 8*0d0.99 = 0d7.92 The nearest real number is 0d8 = 0x8 => overflow of the DIV_frac[2:0] => carry must be added up to the mantissa DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33 Then, USART_BRR = 0x0330 =>...
- Page 615 RM0041 Universal synchronous asynchronous receiver transmitter (USART) Table 126. Error calculation for programmed baud rates at f = 8 MHz or f =12 MHz, PCLK PCLK oversampling by 8 Oversampling by 8 (OVER8 = 1) Baud rate = 8 MHz = 12 MHz PCLK PCLK...
- Page 616 Universal synchronous asynchronous receiver transmitter (USART) RM0041 Table 127. Error calculation for programmed baud rates at f = 16 MHz or f = 24 MHz, PCLK PCLK oversampling by 16 (continued) Oversampling by 16 (OVER8 = 0) Baud rate = 16 MHz = 24 MHz f PCLK f PCLK...
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Page 617: Usart Receiver Tolerance To Clock Deviation
RM0041 Universal synchronous asynchronous receiver transmitter (USART) 23.3.5 USART receiver tolerance to clock deviation The USART asynchronous receiver works correctly only if the total clock system deviation is smaller than the USART receiver’s tolerance. The causes which contribute to the total deviation are: •... -
Page 618: Figure 250. Mute Mode Using Idle Line Detection
Universal synchronous asynchronous receiver transmitter (USART) RM0041 respective TX outputs are logically ANDed together and connected to the RX input of the master. In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant USART service overhead for all non addressed receivers. -
Page 619: Parity Control
RM0041 Universal synchronous asynchronous receiver transmitter (USART) It exits from mute mode when an address character is received which matches the programmed address. Then the RWU bit is cleared and subsequent bytes are received normally. The RXNE bit is set for the address character since the RWU bit has been cleared. -
Page 620: Lin (Local Interconnection Network) Mode
Universal synchronous asynchronous receiver transmitter (USART) RM0041 Odd parity The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. E.g.: data=00110101;... - Page 621 RM0041 Universal synchronous asynchronous receiver transmitter (USART) and are followed by a delimiter character, the LBD flag is set in USART_SR. If the LBDIE bit=1, an interrupt is generated. Before validating the break, the delimiter is checked for as it signifies that the RX line has returned to a high level.
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Page 622: Figure 252. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
Universal synchronous asynchronous receiver transmitter (USART) RM0041 Figure 252. Break detection in LIN mode (11-bit break length - LBDL bit is set) Case 1: break signal not long enough => break discarded, LBD is not set Break frame RX line Capture strobe Break state Idle... -
Page 623: Usart Synchronous Mode
RM0041 Universal synchronous asynchronous receiver transmitter (USART) Figure 253. Break detection in LIN mode vs. Framing error detection Case 1: break occurring after an Idle RX line data 1 IDLE BREAK data 2 (0x55) data 3 (header) 1 data time 1 data time RXNE /FE LBDF... -
Page 624: Figure 254. Usart Example Of Synchronous Transmission
Universal synchronous asynchronous receiver transmitter (USART) RM0041 has been written). This means that it is not possible to receive a synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. -
Page 625: Single-Wire Half-Duplex Communication
RM0041 Universal synchronous asynchronous receiver transmitter (USART) Figure 256. USART data clock timing diagram (M=1) Idle or Idle or next preceding Start M=1 (9 data bits) Stop transmission transmission Clock (CPOL=0, CPHA=0 Clock (CPOL=0, CPHA=1 Clock (CPOL=1, CPHA=0 Clock (CPOL=1, CPHA=1 Data on TX (from master) -
Page 626: Smartcard
Universal synchronous asynchronous receiver transmitter (USART) RM0041 As soon as HDSEL is written to 1: • the TX and RX lines are internally connected • the RX pin is no longer used • the TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. -
Page 627: Figure 259. Parity Error Detection Using The 1.5 Stop Bits
RM0041 Universal synchronous asynchronous receiver transmitter (USART) shifting on the next baud clock edge. In Smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock. • If a parity error is detected during reception of a frame programmed with a 0.5 or 1.5 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame. -
Page 628: Irda Sir Endec Block
Universal synchronous asynchronous receiver transmitter (USART) RM0041 prescaler register USART_GTPR. CK frequency can be programmed from f /2 to f /62, where f is the peripheral input clock. 23.3.12 IrDA SIR ENDEC block The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared: •... -
Page 629: Figure 260. Irda Sir Endec- Block Diagram
RM0041 Universal synchronous asynchronous receiver transmitter (USART) IrDA low-power mode Transmitter: In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz. Generally this value is 1.8432 MHz (1.42 MHz <... -
Page 630: Continuous Communication Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0041 23.3.13 Continuous communication using DMA The USART is capable of continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register. -
Page 631: Figure 262. Transmission Using Dma
RM0041 Universal synchronous asynchronous receiver transmitter (USART) Figure 262. Transmission using DMA Idle preamble Frame 1 Frame 2 Frame 3 TX line set by hardware set by hardware cleared by DMA read cleared by DMA read set by hardware TXE flag ignored by the DMA DMA request because DMA transfer is complete... -
Page 632: Hardware Flow Control
Universal synchronous asynchronous receiver transmitter (USART) RM0041 Figure 263. Reception using DMA Frame 1 Frame 2 Frame 3 TX line set by hardware cleared by DMA read RXNE flag DMA request USART_DR DMA reads USART_DR cleared DMA TCIF flag set by hardware by software (Transfer complete) software configures the... -
Page 633: Figure 265. Rts Flow Control
RM0041 Universal synchronous asynchronous receiver transmitter (USART) RTS flow control If the RTS flow control is enabled (RTSE=1), then RTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, RTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame. -
Page 634: Figure 266. Cts Flow Control
Universal synchronous asynchronous receiver transmitter (USART) RM0041 Figure 266. CTS flow control Transmit data register Data 2 empty Data 3 empty Stop Start Stop Start Idle Data 1 Data 2 Data 3 Writing data 3 in TDR Transmission of Data 3 is delayed until CTS = 0 MSv68793V1 Note:... -
Page 635: Usart Interrupts
RM0041 Universal synchronous asynchronous receiver transmitter (USART) 23.4 USART interrupts Table 132. USART interrupt requests Enable control Interrupt event Event flag Transmit Data Register Empty TXEIE CTS flag CTSIE Transmission Complete TCIE Received Data Ready to be Read RXNE RXNEIE Overrun Error Detected Idle Line Detected IDLE... -
Page 636: Usart Mode Configuration
Universal synchronous asynchronous receiver transmitter (USART) RM0041 23.5 USART mode configuration Table 133. USART mode configuration USART modes USART1 USART2 USART3 UART4 UART5 USART6 Asynchronous mode Hardware Flow Control Multibuffer communication (DMA) Multiprocessor communication Synchronous Smartcard Half-Duplex (Single-Wire mode) IrDA 1. - Page 637 RM0041 Universal synchronous asynchronous receiver transmitter (USART) Bit 7 TXE: Transmit data register empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. It is cleared by a write to the USART_DR register.
- Page 638 Universal synchronous asynchronous receiver transmitter (USART) RM0041 Bit 2 NF: Noise detected flag This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an read to the USART_SR register followed by a read to the USART_DR register).
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Page 639: Data Register (Usart_Dr)
RM0041 Universal synchronous asynchronous receiver transmitter (USART) 23.6.2 Data register (USART_DR) Address offset: 0x04 Reset value: 0xXXXX XXXX Bits 31:9 Reserved, must be kept at reset value Bits 8:0 DR[8:0]: Data value Contains the Received or Transmitted data character, depending on whether it is read from or written to. - Page 640 Universal synchronous asynchronous receiver transmitter (USART) RM0041 Bits 31:16 Reserved, must be kept at reset value Bit 15 OVER8: Oversampling mode 0: oversampling by 16 1: oversampling by 8 Note: Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes: when SCEN=1,IREN=1 or LINEN=1 then OVER8 is forced to ‘0 by hardware.
- Page 641 RM0041 Universal synchronous asynchronous receiver transmitter (USART) Bit 5 RXNEIE: RXNE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An USART interrupt is generated whenever ORE=1 or RXNE=1 in the USART_SR register Bit 4 IDLEIE: IDLE interrupt enable This bit is set and cleared by software.
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Page 642: Control Register 2 (Usart_Cr2)
Universal synchronous asynchronous receiver transmitter (USART) RM0041 23.6.5 Control register 2 (USART_CR2) Address offset: 0x10 Reset value: 0x0000 0000 Reserved LINEN STOP[1:0] CLKEN CPOL CPHA LBCL Res. LBDIE LBDL Res. ADD[3:0] Res. Bits 31:15 Reserved, must be kept at reset value Bit 14 LINEN: LIN mode enable This bit is set and cleared by software. -
Page 643: Control Register 3 (Usart_Cr3)
RM0041 Universal synchronous asynchronous receiver transmitter (USART) Bit 8 LBCL: Last bit clock pulse This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the CK pin 1: The clock pulse of the last data bit is output to the CK pin Note: 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected... - Page 644 Universal synchronous asynchronous receiver transmitter (USART) RM0041 Bit 6 DMAR: DMA enable receiver This bit is set/reset by software 1: DMA mode is enabled for reception 0: DMA mode is disabled for reception Bit 5 SCEN: Smartcard mode enable This bit is used for enabling Smartcard mode. 0: Smartcard mode disabled 1: Smartcard mode enabled Bit 4 NACK: Smartcard NACK enable...
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Page 645: Guard Time And Prescaler Register (Usart_Gtpr)
RM0041 Universal synchronous asynchronous receiver transmitter (USART) 23.6.7 Guard time and prescaler register (USART_GTPR) Address offset: 0x18 Reset value: 0x0000 0000 Reserved GT[7:0] PSC[7:0] Bits 31:16 Reserved, must be kept at reset value Bits 7:0 PSC[7:0]: Prescaler value – In IrDA Low-power mode: PSC[7:0] = IrDA Low-Power Baud Rate Used for programming the prescaler for dividing the system clock to achieve the low-power frequency:... -
Page 646: Usart Register Map
Universal synchronous asynchronous receiver transmitter (USART) RM0041 23.6.8 USART register map The table below gives the USART register map and reset values. Table 134. USART register map and reset values Offset Register USART_SR 0x00 Reserved Reset value USART_DR DR[8:0] 0x04 Reserved Reset value DIV_Fraction... -
Page 647: High-Definition Multimedia Interface-Consumer Electronics Control Controller (Hdmi™-Cec)
RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™- High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. -
Page 648: Hdmi-Cec Main Features
High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) 24.2 HDMI-CEC main features • Supports HDMI-CEC v1.3a • Supports the whole set of features offered with CEC (devices may use all or only some of these features, depending on functionality): – One touch play - a device may be played and become the active source by pressing a single button. -
Page 649: Message Description
RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™- Table 135. HDMI pin Name Signal type Remarks Two states: 1 = high impedance Bidirectional 0 = low impedance Ω A 27 k pull-up resistor must be added externally. Figure 268. CEC line connection 3.3 V HDMI_CEC CEC_RX... -
Page 650: Bit Timing
High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) The acknowledge bit is always set to high impedance by the initiator so that it can be driven low either by the follower that has read its own address in the header or by the follower that needs to reject a broadcast message. -
Page 651: Arbitration
RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™- Figure 272. Follower acknowledge (ACK) 2.4 ±0.35 ms 0.6 ±0.2 ms high impedance low impedance Data bit initiator logical 1 2.4 ±0.35 ms 0.35 ms max. high impedance low impedance Data bit follower logical 0 ai17767 24.4 Arbitration... -
Page 652: Error Handling
High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) continues until the end of the initiator address bits within the header block. During the header transmission period the initiator monitors the CEC line and if it detects a low impedance while it is in the high impedance state, then it assumes that it has lost the arbitration to a second initiator. -
Page 653: Hdmi-Cec Functional Description
RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™- the transmitted message. All CEC devices therefore have both a physical and a logical address, whereas non-CEC devices only have a physical address. Once their physical and logical addresses are known, each CEC device transmits them to all other devices, thus allowing any device to create a map of the network. -
Page 654: Rx Digital Filter
High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) 24.7.3 Rx digital filter CEC robustness in the face of CEC line perturbation is guaranteed by two noise rejection mechanisms: • high-frequency spikes are removed by a 2/3 majority voter applied on the Rx line sampled at the system clock rate •... -
Page 655: Tx Bit Timing
RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™- Table 137. Bit status depending on the low bit duration (LBD) Low bit duration (LBD) Standard mode Bit timing error-free (ms) (BTEM = 0) (BTEM = 1) < 0 ≤ LBD Bit timing error ≤... -
Page 656: Cec Arbiter
High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) 24.7.6 CEC arbiter The STM32F100xx CEC arbiter declines SFT and header arbitration techniques in the following cases: • CEC is a previous initiator retrying a failed transmission and the leading edge of the start bit is detected before SFT = 9.6 ms. This only occurs when a new initiator violates the SFT requirement. -
Page 657: Cec States
RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™- 24.7.7 CEC states Figure 279 shows the CEC controller state machine. Figure 279. CEC control state machine Reset Disabled PE = 0 PE = 1 Idle TSOM = 1 Start bit & TSOM = 0 Arbitration lost TEOM = 1 TERR = 1... -
Page 658: Table 140. Software Sequence To Respect When Receiving A Message
High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) status register. The host CPU can either poll this register or enable interrupts in the configuration status register to know whether a byte was received. If the RBTF bit is not cleared by the time a new block is received, the newly received block is not acknowledged to force the initiator to restart the message transmission, thus giving the host CPU a second chance to retrieve all message bytes in time. -
Page 659: Table 141. Software Sequence To Respect When Transmitting A Message
RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™- TX state The controller enters the TX state when the TSOM bit is set in the control status register. In this state, it has to make sure that the required signal free time elapses before generating a start bit. -
Page 660: Figure 282. Example Of A Message Transmission With Transmission Error
High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) Table 141. Software sequence to respect when transmitting a message (continued) Status bits CEC_CSR R/W Software sequences TBTRF TERR TEOM TSOM access bit 3 bit 2 bit 1 bit 0 Write Operand1 to TX buffer Acknowledge byte request by writing 0x00 Write 0x00 Poll TBTRF or wait until an interrupt occurs... -
Page 661: Cec And System Stop Mode
RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™- The software must respect the following sequence in case of a transmission error: Table 142. Software sequence to respect when transmitting a message Status bits CEC_CSR R/W Software sequences TBTRF TERR TEOM TSOM access bit 3... -
Page 662: Hdmi-Cec Interrupts
High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) when the current frame (if any) transmission is complete. Once PE is cleared, the HDMI-CEC peripheral is disabled and the CEC line signal is ignored. This operation ensures that the device safely enters the system Stop mode. Otherwise the system clock might stop while the CEC device is in the low impedance state, for example during a handshake bit. -
Page 663: Hdmi-Cec Registers
RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™- 24.9 HDMI-CEC registers Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 24.9.1 CEC configuration register (CEC_CFGR) This register is used to configure the HDMI-CEC controller. -
Page 664: Cec Own Address Register (Cec_Oar)
High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) 24.9.2 CEC own address register (CEC_OAR) This register is written by the software to define the address of the CEC device. Address offset: 0x4 Reset value: 0x0000 0000 Reserved OA[3:0] Reserved Bits 31:4 Reserved, must be kept cleared. Bits 3:0 OA[3:0]: Own address These bits are written by software to define the own address of the CEC device. -
Page 665: Cec Error Status Register (Cec_Esr)
RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™- 24.9.4 CEC error status register (CEC_ESR) CEC_ESR is the CEC error status register. It contains all the error flags related to the communication. Address offset: 0x0C Reset value: 0x0000 0000 Reserved TBTFE LINE ACKE RBTFE... -
Page 666: Cec Control And Status Register (Cec_Csr)
High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) 24.9.5 CEC control and status register (CEC_CSR) CEC_CSR is the CEC control & status register. It contains all the flags related to the communication and some control bits to be managed during the communication. Address offset: 0x10 Reset value: 0x0000 0000 Reserved... -
Page 667: Cec Tx Data Register (Cec_Txd)
RM0041 High-definition multimedia interface-consumer electronics control controller (HDMI™- Bit 2 TERR: Tx error This bit is set by hardware when a transmission error occurs. The software can read the CEC_ESR register to better know which error occurred. If the IE bit in the CEC_CFGR register is set, an interrupt is generated. -
Page 668: Hdmi-Cec Register Map
High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) 24.9.8 HDMI-CEC register map The following table summarizes the HDMI-CEC registers. Table 144. HDMI-CEC register map and reset values Offset Register CEC_CFGR 0x00 Reserved Reset value CEC_OAR OAR[3:0] 0x04 Reserved Reset value CEC_PRE PRESC[13:0] 0x08 Reserved... -
Page 669: Debug Support (Dbg)
RM0041 Debug support (DBG) Debug support (DBG) Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 670: Figure 284. Block Diagram Of Stm32 Mcu And Cortex
Debug support (DBG) RM0041 ® Figure 284. Block diagram of STM32 MCU and Cortex -M3-level debug support STM32F100xx debug sup port Cortex-M3 debug s uppo rt Bus matrix DCode interface Data Cortex-M3 System core interface JTMS/ SWDIO External private TRACESWO peripheral bus (PPB) JTDI Trace port... -
Page 671: Reference Arm® Documentation
RM0041 Debug support (DBG) ® 25.2 Reference Arm documentation ® • Cortex -M3 r1p1 Technical Reference Manual (TRM) It is available from: http://infocenter.arm.com/ ® • Debug Interface V5 ® • CoreSight Design Kit revision r1p1 Technical Reference Manual 25.3 SWJ debug port (serial wire and JTAG) The core of the STM32F100xx integrates the Serial Wire / JTAG Debug Port (SWJ-DP). -
Page 672: Mechanism To Select The Jtag-Dp Or The Sw-Dp
Debug support (DBG) RM0041 25.3.1 Mechanism to select the JTAG-DP or the SW-DP By default, the JTAG-Debug Port is active. If the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG sequence on TMS/TCK (respectively mapped to SWDIO and SWCLK) which disables the JTAG-DP and enables the SW-DP. -
Page 673: Internal Pull-Up And Pull-Down On Jtag Pins
RM0041 Debug support (DBG) Three control bits allow the configuration of the SWJ-DP pin assignments. These bits are reset by the System Reset. • AFIO_MAPR (@ 0x40010004 in the STM32F100xx MCU) – READ: APB - No Wait State – WRITE: APB - 1 Wait State if the write buffer of the AHB-APB bridge is full. Bit 26:24= SWJ_CFG[2:0] Set and cleared by software. - Page 674 Debug support (DBG) RM0041 Once a JTAG IO is released by the user software, the GPIO controller takes control again. The reset states of the GPIO control registers put the I/Os in the equivalent state: • NJTRST: Input pull-up • JTDI: Input pull-up •...
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Page 675: Using Serial Wire And Releasing The Unused Debug Pins As Gpios
RM0041 Debug support (DBG) 25.4.4 Using serial wire and releasing the unused debug pins as GPIOs To use the serial wire DP to release some GPIOs, the user software must set SWJ_CFG=010 just after reset. This releases PA15, PB3 and PB4 which now become available as GPIOs. -
Page 676: Figure 286. Jtag Tap Connections
Debug support (DBG) RM0041 Figure 286. JTAG TAP connections STM32F100xx NJTRST JTMS SW-DP selected TMS nTRST nTRST JTDI Boundary scan Cortex-M3 TAP IR is 5-bit wide IR is 4-bit wide JTDO ai17306 676/709 RM0041 Rev 6... -
Page 677: Id Codes And Locking Mechanism
25.6.1 MCU device ID code The STM32F100xx MCUs integrate an MCU ID code. This ID identifies the ST MCU part- number and the die revision. It is part of the DBG_MCU component and is mapped on the external PPB bus (see Section 25.15). -
Page 678: Boundary Scan Tap
Debug support (DBG) RM0041 25.6.2 Boundary scan TAP JTAG ID code The TAP of the STM32F100xx BSC (boundary scan) integrates a JTAG ID code equal to • In low and medium-density value line devices: – 0x06420041 = Revision A and Revision Z •... -
Page 679: Table 148. 32-Bit Debug Port Registers Addressed Through The Shifted Value A[3:2]
RM0041 Debug support (DBG) Table 147. JTAG debug port data registers (continued) IR(3:0) Data register Details Access port access register Initiates an access port and allows access to an access port register. – When transferring data IN: Bits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request Bits 2:1 = A[3:2] = 2-bit address (sub-address AP registers). -
Page 680: Sw Debug Port
Debug support (DBG) RM0041 25.8 SW debug port 25.8.1 SW protocol introduction This synchronous serial protocol uses two pins: • SWCLK: clock from host to target • SWDIO: bidirectional The protocol allows two banks of registers (DPACC registers and APACC registers) to be read and written to. -
Page 681: Sw-Dp State Machine (Reset, Idle States, Id Code)
RM0041 Debug support (DBG) Table 150. ACK response (3 bits) Name Description 001: FAULT 0..2 010: WAIT 100: OK The ACK Response must be followed by a turnaround time only if it is a READ transaction or if a WAIT or FAULT acknowledge has been received. Table 151. -
Page 682: Sw-Dp Registers
Access to these registers are initiated when APnDP=0 Table 152. SW-DP registers CTRLSEL bit A[3:2] of SELECT Register Notes register The manufacturer code is not set to ST code. Read IDCODE 0x1BA01477 (identifies the SW-DP) Write ABORT Purpose is to: – request a system or debug power-up –... -
Page 683: Ahb-Ap (Ahb Access Port) - Valid For Both Jtag-Dp And Sw-Dp
RM0041 Debug support (DBG) 25.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP Features: • System access is independent of the processor status. • Either SW-DP or JTAG-DP accesses AHB-AP. • The AHB-AP is an AHB master into the Bus Matrix. Consequently, it can access all the data buses (Dcode Bus, System Bus, internal and external PPB bus) but the ICode bus. -
Page 684: Core Debug
Debug support (DBG) RM0041 25.10 Core debug Core debug is accessed through the core debug registers. Debug access to these registers is by means of the Advanced High-performance Bus (AHB-AP) port. The processor can access these registers directly over the internal Private Peripheral Bus (PPB). It consists of 4 registers: Table 154. -
Page 685: Capability Of The Debugger Host To Connect Under System Reset
RM0041 Debug support (DBG) 25.11 Capability of the debugger host to connect under system reset The reset system of the STM32F100xx MCU comprises the following reset sources: • POR (power-on reset) which asserts a RESET at each power-up. • Internal watchdog reset •... -
Page 686: Dwt (Data Watchpoint Trigger)
Debug support (DBG) RM0041 25.13 DWT (data watchpoint trigger) The DWT unit consists of four comparators. They are configurable as: • a hardware watchpoint or • a PC sampler or • a data address sampler The DWT also provides some means to give some profiling informations. For this, some counters are accessible to give the number of: •... -
Page 687: Table 155. Main Itm Registers
RM0041 Debug support (DBG) For this, the DWT must be configured to trigger the ITM: the bit CYCCNTENA (bit0) of the DWT Control register must be set. In addition, the bit2 (SYNCENA) of the ITM Trace Control register must be set. Note: If the SYNENA bit is not set, the DWT generates Synchronization triggers to the TPIU which sends only TPIU synchronization packets and not ITM synchronization packets. -
Page 688: Mcu Debug Component (Dbgmcu)
Debug support (DBG) RM0041 Example of configuration To output a simple value to the TPIU: • Configure the TPIU and assign TRACE I/Os by configuring the DBGMCU_CR (refer to Section 25.16.2 Section 25.15.3) • Write 0xC5ACCE55 to the ITM Lock Access register to unlock the write access to the ITM registers •... -
Page 689: Debug Mcu Configuration Register
RM0041 Debug support (DBG) For timers having complementary outputs, when the counter is stopped (DBG_TIMx_STOP = 1), the outputs are disabled (as if the MOE bit was reset) for safety purposes. 25.15.3 Debug MCU configuration register This register allows the configuration of the MCU under DEBUG. This concerns: •... - Page 690 Debug support (DBG) RM0041 Bits 20:18 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=5 .. 7) 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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Page 691: Tpiu (Trace Port Interface Unit)
RM0041 Debug support (DBG) Bit 2 DBG_STANDBY: Debug Standby mode 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. From software point of view, exiting from Standby is identical than fetching reset vector (except a few status bit indicated that the MCU is resuming from Standby) 1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active. -
Page 692: Figure 287. Tpiu Block Diagram
Debug support (DBG) RM0041 Figure 287. TPIU block diagram TRACECLKIN domain CLK domain TPIU TRACECLKIN TRACECK Asynchronous TPIU Trace out FIFO TRACEDATA formatter (serializer) [3:0] TRACESWO External PPB bus ai17307 692/709 RM0041 Rev 6... -
Page 693: Trace Pin Assignment
RM0041 Debug support (DBG) 25.16.2 TRACE pin assignment • Asynchronous mode The asynchronous mode requires 1 extra pin and is available on all packages. It is only available if using Serial Wire mode (not in JTAG mode). Table 156. Asynchronous TRACE pin assignment Trace synchronous mode STM32F100xx pin TPUI pin name... -
Page 694: Tpui Formatter
Debug support (DBG) RM0041 Table 158. Flexible TRACE pin assignment DBGMCU_CR TRACE IO pin assigned register Pins assigned TRACE TRACE PB3 /JTDO/ PE2/ PE3 / PE4 / PE5 / PE6 / for: _MODE _IOEN TRACESWO TRACECK TRACED[0] TRACED[1] TRACED[2] TRACED[3] [1:0] No Trace Released... -
Page 695: Tpui Frame Synchronization Packets
RM0041 Debug support (DBG) ® ® Note: Refer to the Arm CoreSight Architecture Specification v1.0 (Arm IHI 0029B) for further information 25.16.4 TPUI frame synchronization packets The TPUI can generate two types of synchronization packets: • The Frame Synchronization packet (or Full Word Synchronization packet) It consists of the word: 0x7F_FF_FF_FF (LSB emitted first). -
Page 696: Asynchronous Mode
Debug support (DBG) RM0041 25.16.7 Asynchronous mode This is a low cost alternative to output the trace using only 1 pin: this is the asynchronous output pin TRACESWO. Obviously there is a limited bandwidth. TRACESWO is multiplexed with JTDO when using the SW-DP pin. This way, this functionality is available in all STM32F100xx packages. -
Page 697: 25.16.10 Example Of Configuration
RM0041 Debug support (DBG) Table 159. Important TPIU registers (continued) Address Register Description Bits 31-9 = always ‘0 Bit 8 = TrigIn = always ‘1 to indicate that triggers are indicated Bits 7-4 = always 0 Bits 3-2 = always 0 Bit 1 = EnFCont. -
Page 698: Dbg Register Map
Debug support (DBG) RM0041 25.17 DBG register map The following table summarizes the Debug registers. Table 160. Value DBG register map and reset values Addr. Register DBGMCU_ DEV_ID REV_ID IDCODE Reserved Reset value DBGMCU_ Reserved Reset value 1. The reset value is product dependent. For more information, refer to Section 25.6.1: MCU device ID code. -
Page 699: Device Electronic Signature
RM0041 Device electronic signature Device electronic signature Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes. Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes. High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes. -
Page 700: Unique Device Id Register (96 Bits)
Device electronic signature RM0041 26.2 Unique device ID register (96 bits) The unique device identifier is ideally suited: • for use as serial numbers • for use as security keys, to increase the security of code in flash memory while using and combining this unique ID with software cryptographic primitives and protocols, before programming the internal flash memory •... - Page 701 RM0041 Device electronic signature Address offset: 0x08 Read only = 0xXXXX XXXX where X is factory-programmed U_ID(95:80) U_ID(79:64) Bits 31:0 U_ID(95:64): 95:64 unique ID bits. RM0041 Rev 6 701/709...
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Page 702: Important Security Notice
ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. -
Page 703: Revision History
RM0041 Revision history Revision history Table 161. Document revision history Date Revision Changes 26-Feb-2010 Initial release. Corrected description of TIMx_CCER register in Section 12.4.9 on page Section 13.4.9 on page 334 Updated Section 14.3.5: Input capture mode on page 353 04-Jun-2010 Added method 1 and 2 in Section 22.3.3: I2C master mode... - Page 704 Revision history RM0041 Table 161. Document revision history (continued) Date Revision Changes I2C: Updated BERR bit description in Section 22.6.6: I C Status register 1 (I2C_SR1). Updated Note: Section 22.6.8: I C Clock control register (I2C_CCR). Added note 3 below Figure 235: Transfer sequence diagram for slave transmitter on page 570.
- Page 705 RM0041 Revision history Table 161. Document revision history (continued) Date Revision Changes Updated: – Introduction – Section 2.1: System architecture, Section 2.3: Memory map – Section 25.6.1: MCU device ID code. – Section 4.4.2: Power control/status register (PWR_CSR), – Section 6.1.2: Power reset, Section 6.2.8: RTC clock –...
- Page 706 Revision history RM0041 Table 161. Document revision history (continued) Date Revision Changes Updated: – Mode 1 - SRAM/PSRAM (CRAM), Asynchronous static memories (NOR flash memory, PSRAM, SRAM), , Mode 2/B - NOR flash, SRAM/NOR- Flash chip-select timing registers 1..4 (FSMC_BTR1..4), SRAM/NOR- Flash write timing registers 1..4 (FSMC_BWTR1..4),...
- Page 707 Index RM0041 Index DAC_DHR12R1 ..... . 205 DAC_DHR12R2 ..... . 207 ADC_CR1 .
- Page 708 RM0041 Index I2C_DR ......591 TIM15_BDTR ......431 I2C_OAR1 .
- Page 709 ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
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