Usart Mode Configuration; Usart Registers; Status Register (Usart_Sr); Table 156. Usart Modes Configuration - ST STM32F102 Series Reference Manual

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Table of Contents

Universal synchronous asynchronous receiver transmitter (USART)

USART mode configuration

Asynchronous mode

Hardware Flow Control

Multibuffer Communication (DMA)

Multiprocessor Communication

Half-Duplex (Single-Wire mode)

1. X = supported; NA = not applicable.

Address offset: 0x00

Reset value: 0x00C0

Bits 31:10 Reserved, forced by hardware to 0.

Bit 9 CTS: CTS Flag

This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by

software (by writing it to 0). An interrupt is generated if CTSIE=1 in the USART_CR3 register.

0: No change occurred on the nCTS status line

1: A change occurred on the nCTS status line

Note: This bit is not available for UART4 & UART5.

Bit 8 LBD: LIN Break Detection Flag

This bit is set by hardware when the LIN break is detected. It is cleared by software (by writing it to

0). An interrupt is generated if LBDIE = 1 in the USART_CR2 register.

0: LIN Break not detected

1: LIN break detected

Note: An interrupt is generated when LBD=1 if LBDIE=1

Section 1.1 on page 32

for a list of abbreviations used in register descriptions.

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