Fast Interleaved Mode; Slow Interleaved Mode; Figure 30. Regular Simultaneous Mode On 16 Channels; Figure 31. Fast Interleaved Mode On 1 Channel In Continuous Conversion Mode - ST STM32F102 Series Reference Manual

Hide thumbs Also See for STM32F102 Series:

Table of Contents

Fast interleaved mode

This mode can be started only on a regular channel group (usually one channel). The

source of external trigger comes from the regular channel mux of ADC1. After an external

trigger occurs:

ADC2 starts immediately and

ADC1 starts after a delay of 7 ADC clock cycles.

If CONT bit is set on both ADC1 and ADC2 the selected regular channels of both ADCs are

continuously converted.

After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit

DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the

ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the

ADC1 converted data in the lower halfword.

The maximum sampling time allowed is <7 ADCCLK cycles to avoid the overlap between

ADC1 and ADC2 sampling phases in the event that they convert the same channel.

This mode can be started only on a regular channel group (only one channel). The source of

external trigger comes from regular channel mux of ADC1. After external trigger occurs:

ADC2 starts immediately and

ADC1 starts after a delay of 14 ADC clock cycles.

ADC2 starts after a second delay of 14 ADC cycles, and so on.

The maximum sampling time allowed is <14 ADCCLK cycles to avoid an overlap with the

next conversion.

End of conversion on ADC2

End of conversion on ADC1

Analog-to-digital converter (ADC)

End of conversion on ADC1 and ADC2

Do you have a question about the STM32F102 Series and is the answer not in the manual?

Stm32f101 series Stm32f103 series