Figure 63. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 64. Counter Timing Diagram, Internal Clock Divided By N; Figure 65. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow); Figure 111. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36 - ST STM32F102 Series Reference Manual

General-purpose timer (TIMx)

Figure 111. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow

Figure 112. Counter timing diagram, internal clock divided by N

Figure 113. Counter timing diagram, Update event with ARPE=1 (counter underflow)

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CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow (cnt_ovf)
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
0034
0035
20 1F 01
06 05 04 03 02 01 00 01 02 03 04 05 06 07
FD
FD
RM0008
0036 0035
00
36
36