Dual Dac 12-Bit Left Aligned Data Holding Register; (Dac_Dhr12Ld); Dual Dac 8-Bit Right Aligned Data Holding Register; (Dac_Dhr8Rd) - ST STM32F102 Series Reference Manual

RM0008
11.5.10

DUAL DAC 12-bit Left aligned Data Holding Register

(DAC_DHR12LD)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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DACC2DHR[11:0]: DAC channel2 12-bit Left aligned data
Bits 31:20
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 19:16 Reserved.
DACC1DHR[11:0]: DAC channel1 12-bit Left aligned data
Bits 15:4
These bits are written by software which specify 12-bit data for DAC channel1.
Bits 3:0 Reserved.
11.5.11

DUAL DAC 8-bit Right aligned Data Holding Register

(DAC_DHR8RD)

Address offset: 0x28
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
DACC2DHR[7:0]
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Bits 31:16 Reserved.
DACC2DHR[7:0]: DAC channel2 8-bit Right aligned data
Bits 15:8
These bits are written by software which specify 8-bit data for DAC channel2
DACC1DHR[7:0]: DAC channel1 8-bit Right aligned data
Bits 7:0
These bits are written by software which specify 8-bit data for DAC channel1
27 26 25
DACC2DHR[11:0]
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11 10 9
DACC1DHR[11:0]
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27 26 25
11 10 9
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Digital-to-analog converter (DAC)
24 23 22 21
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8 7 6 5
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24 23 22 21
Reserved
8 7 6 5
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20 19 18 17
Reserved
rw
4 3 2
Reserved
rw
20 19 18 17
4 3 2
DACC1DHR[7:0]
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.
.
16
1 0
16
1 0
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