Usb Registers; Common Registers - ST STM32F102 Series Reference Manual

RM0008
In this case, the resume sequence can be started by setting the RESUME bit in the
USB_CNTR register to '1' and resetting it to 0 after an interval between 1mS and 15mS (this
interval can be timed using ESOF interrupts, occurring with a 1mS period when the system
clock is running at nominal frequency). Once the RESUME bit is clear, the resume
sequence will be completed by the host PC and its end can be monitored again using the
RXDP and RXDM bits in the USB_FNR register.
Note: The RESUME bit must be anyway used only after the USB peripheral has been put in
suspend mode, setting the FSUSP bit in USB_CNTR register to 1.
20.5

USB registers

The USB peripheral registers can be divided into the following groups:
●
Common Registers: Interrupt and Control registers
●
Endpoint Registers: Endpoint configuration and status
●
Buffer Descriptor Table: Location of packet memory used to locate data buffers
All register addresses are expressed as offsets with respect to the USB peripheral registers
base address 0x4000 5C00, except the buffer descriptor table locations, which starts at the
address specified by the USB_BTABLE register. Due to the common limitation of APB1
bridges on word addressability, all register addresses are aligned to 32-bit word boundaries
although they are 16-bit wide. The same address alignment is used to access packet buffer
memory locations, which are located starting from 0x4000 6000.
Refer to
20.5.1

Common registers

These registers affect the general behavior of the USB peripheral defining operating mode,
interrupt handling, device address and giving access to the current frame number updated
by the host PC.
USB control register (USB_CNTR)
Address offset: 0x40
Reset value: 0x0003
15 14 13
PMAO WKUP
CTRM ERRM
VRM
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Section 1.1 on page 32
12 11 10 9
SUSP RESE
SOFM
M M TM
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USB full speed device interface (USB)
for a list of abbreviations used in register descriptions.
8 7 6
ESOF
Reserved
M
rw Res.
5 4 3 2
RESU FSUS LP_M
ME P ODE
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1 0
PDWN FRES
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