ST STM32F102 Series Reference Manual page 672

Debug support (DBG)
Bit 14 DBG_CAN_STOP: Debug CAN stopped when Core is halted
0: Same behavior as in normal mode.
1: The CAN receive registers are frozen.
Bits 13:10 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=4..1)
0: The clock of the involved Timer Counter is fed even if the core is halted.
1: The clock of the involved Timer counter is stopped when the core is halted.
Bit 9 DBG_WWDG_STOP: Debug Window Watchdog stopped when Core is halted
0: The Window Watchdog Counter clock continues even if the core is halted.
1: The Window Watchdog Counter clock is stopped when the core is halted.
Bit 8 DBG_IWDG_STOP: Debug Independent Watchdog stopped when Core is halted
0: The Watchdog counter clock continues even if the core is halted.
1: The Watchdog counter clock is stopped when the core is halted.
Bits 7:5 TRACE_MODE[1:0] and TRACE_IOEN: Trace Pin Assignment Control
– With TRACE_IOEN=0:
TRACE_MODE=xx: TRACE pins not assigned (default state)
– With TRACE_IOEN=1:
TRACE_MODE=00: TRACE pin assignment for Asynchronous Mode
TRACE_MODE=01: TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1
TRACE_MODE=10: TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2
TRACE_MODE=11: TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4
Bit 4:3 Reserved, must be kept cleared.
Bit 2 DBG_STANDBY: Debug Standby mode
0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
From software point of view, exiting from Standby is identical than fetching reset vector (except a few
status bit indicated that the MCU is resuming from Standby)
1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and HCLK are
provided by the internal RC oscillator which remains active. In addition, the MCU generate a system
reset during Standby mode so that exiting from Standby is identical than fetching from reset
Bit 1 DBG_STOP: Debug Stop Mode
0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including HCLK
and FCLK). When exiting from STOP mode, the clock configuration is identical to the one after
RESET (CPU clocked by the 8 MHz internal RC oscillator (HSI)). Consequently, the software must
reprogram the clock controller to enable the PLL, the Xtal, etc.
1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and HCLK are provided by
the internal RC oscillator which remains active in STOP mode. When exiting STOP mode, the
software must reprogram the clock controller to enable the PLL, the Xtal, etc. (in the same way it
would do in case of DBG_STOP=0)
Bit 0 DBG_SLEEP: Debug Sleep Mode
0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as previously
configured by the software while HCLK is disabled.
In Sleep mode, the clock controller configuration is not reset and remains in the previously
programmed state. Consequently, when exiting from Sleep mode, the software does not need to
reconfigure the clock controller.
1: (FCLK=On, HCLK=On) In this case, when entering Sleep mode, HCLK is fed by the same clock
that is provided to FCLK (system clock as previously configured by the software).
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