I 2 C Interrupts; Table 150. I2C Interrupt Requests - ST STM32F102 Series Reference Manual

RM0008
●
If DMA and PEC calculation are both enabled:-
–
–
●
To allow intermediate PEC transfers, a control bit is available in the I2C_CR2 register
(LAST bit) to determine if it is really the last DMA transfer or not. If it is the last DMA
request for a master receiver, a NACK is automatically sent after the last received byte.
● PEC calculation is corrupted by an arbitration loss.
2
23.4 I C interrupts
The table below gives the list of I
Table 150. I
Start bit sent (Master)
Address sent (Master) or Address matched (Slave)
10-bit header sent (Master)
Stop received (Slave)
Data Byte Transfer Finished
Receive buffer not empty
Transmit buffer empty
Bus error
Arbitration loss (Master)
Acknowledge failure
Overrun/Underrun
PEC error
Timeout/Tlow error
SMBus Alert
Note: 1 SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically ORed on the same interrupt
channel.
2 BERR, ARLO, AF, OVR, PECERR, TIMEOUT and SMBALERT are logically ORed on the
same interrupt channel.
In transmission: when the I
controller, it automatically sends a PEC after the last byte.
In reception: when the I
controller, it will automatically consider the next byte as a PEC and will check it. A
DMA request is generated after PEC reception.
2
C Interrupt requests
Interrupt event
Inter-integrated circuit (I
2
C interface receives an EOT signal from the DMA
2
C interface receives an EOT_1 signal from the DMA
2
C interrupt requests.
2
C) interface
Enable
Event flag
Control bit
SB
ADDR
ADD10 ITEVFEN
STOPF
BTF
RxNE
ITEVFEN and
ITBUFEN
TxE
BERR
ARLO
AF
OVR ITERREN
PECERR
TIMEOUT
SMBALERT
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