Spi Control Register 2 (Spi_Cr2) - ST STM32F102 Series Reference Manual

Serial peripheral interface (SPI)
22.5.2

SPI control register 2 (SPI_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13 12
Bits 15:8 Reserved. Forced to 0 by hardware.
Bit 7 TXEIE: Tx buffer Empty Interrupt Enable
0: TXE interrupt masked
1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.
Note: To function correctly, the TXEIE and TXDMAEN bits should not be set at the same time.
Bit 6 RXNEIE: RX buffer Not Empty Interrupt Enable
0: RXNE interrupt masked
1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set.
Note: To function correctly, the RXNEIE and RXDMAEN bits should not be set at the same time.
Bit 5 ERRIE: Error Interrupt Enable
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR,
MODF in SPI mode and UDR, OVR in I
0: Error interrupt is masked
1: Error interrupt is enabled.
Bits 4:3 Reserved. Forced to 0 by hardware.
Bit 2 SSOE: SS Output Enable
0: SS output is disabled in master mode and the cell can work in multimaster configuration
1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work in a
multimaster environment.
Note: Not used in I
Bit 1 TXDMAEN: Tx Buffer DMA Enable
When this bit is set, the DMA request is made whenever the TXE flag is set.
0: Tx buffer DMA disabled
1: Tx buffer DMA enabled
Bit 0 RXDMAEN: Rx Buffer DMA Enable
When this bit is set, the DMA request is made whenever the RXNE flag is set.
0: Rx buffer DMA disabled
1: Rx buffer DMA enabled
572/690
11 10 9
Reserved
Res.
2
S mode
8 7 6 5
RXNE
TXEIE ERRIE
IE
rw rw rw
2
S mode).
4 3 2 1
TXDMA
reserved SSOE
EN
Res. rw rw
RM0008
0
RXDMA
EN
rw