ST STM32F102 Series Reference Manual page 487

RM0008
Bit 10 RESET: USB RESET request
Set when the USB peripheral detects an active USB RESET signal at its inputs. The USB peripheral,
in response to a RESET, just resets its internal protocol state machine, generating an interrupt if
RESETM enable bit in the USB_CNTR register is set. Reception and transmission are disabled until
the RESET bit is cleared. All configuration registers do not reset: the microcontroller must explicitly
clear these registers (this is to ensure that the RESET interrupt can be safely delivered, and any
transaction immediately followed by a RESET can be completed). The function address and
endpoint registers are reset by an USB reset event.
This bit is read/write but only '0' can be written and writing '1' has no effect.
Bit 9 SOF: Start Of Frame
This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through
the USB bus. The interrupt service routine may monitor the SOF events to have a 1mS
synchronization event to the USB host and to safely read the USB_FNR register which is updated at
the SOF packet reception (this could be useful for isochronous applications). This bit is read/write but
only '0' can be written and writing '1' has no effect.
Bit 8 ESOF: Expected Start Of Frame
This bit is set by the hardware when an SOF packet is expected but not received. The host sends an
SOF packet each mS, but if the hub does not receive it properly, the Suspend Timer issues this
interrupt. If three consecutive ESOF interrupts are generated (i.e. three SOF packets are lost)
without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the
missing SOF packets occur while the Suspend Timer is not yet locked. This bit is read/write but only
'0' can be written and writing '1' has no effect.
Bits 7:5 Reserved.
Bit 4 DIR: Direction of transaction.
This bit is written by the hardware according to the direction of the successful transaction, which
generated the interrupt request.
If DIR bit=0, CTR_TX bit is set in the USB_EPnR register related to the interrupting endpoint. The
interrupting transaction is of IN type (data transmitted by the USB peripheral to the host PC).
If DIR bit=1, CTR_RX bit or both CTR_TX/CTR_RX are set in the USB_EPnR register related to the
interrupting endpoint. The interrupting transaction is of OUT type (data received by the USB
peripheral from the host PC) or two pending transactions are waiting to be processed.
This information can be used by the application software to access the USB_EPnR bits related to the
triggering transaction since it represents the direction having the interrupt pending. This bit is read-
only.
Bits 3:0 EP_ID[3:0]: Endpoint Identifier.
These bits are written by the hardware according to the endpoint number, which generated the
interrupt request. If several endpoint transactions are pending, the hardware writes the endpoint
identifier related to the endpoint having the highest priority defined in the following way: Two endpoint
sets are defined, in order of priority: Isochronous and double-buffered bulk endpoints are considered
first and then the other endpoints are examined. If more than one endpoint from the same set is
requesting an interrupt, the EP_ID bits in USB_ISTR register are assigned according to the lowest
requesting endpoint register, EP0R having the highest priority followed by EP1R and so on. The
application software can assign a register to each endpoint according to this priority scheme, so as
to order the concurring endpoint requests in a suitable way. These bits are read only.
USB full speed device interface (USB)
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