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ST STM32F101xx Reference Manual

Arm-based 32-bit mcus

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Download this manual See also: Programming Manual, Reference Manual

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx

and STM32F107xx advanced ARM-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32F101xx, STM32F102xx, STM32F103xx and

STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx,

STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as

STM32F10xxx throughout the document, unless otherwise specified.

The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and

peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

low-, medium- and high-density STM32F101xx and STM32F103xx datasheets, to the low-

and medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx

connectivity line datasheet.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM32F10xxx Flash programming manual.

For information on the ARM Cortex™-M3 core, please refer to the Cortex™-M3 Technical

Reference Manual.

Related documents

Available from www.arm.com:

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Cortex™-M3 Technical Reference Manual, available from:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/DDI0337E_cortex_m3_r1p1_trm.pdf

Available from www.st.com:

■

STM32F101xx STM32F103xx datasheets

■

STM32F10xxx Flash programming manual

March 2009

Reference manual

Rev 1

RM0034

1/959

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Summary of Contents for ST STM32F101xx

Page 1 The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the low-, medium- and high-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx connectivity line datasheet.
Page 2: Table Of Contents
Contents RM0034 Contents Documentation conventions ....... . . 36 List of abbreviations for registers ....... 36 Glossary .
Page 3 RM0034 Contents 4.3.1 Slowing down system clocks ....... . . 55 4.3.2 Peripheral clock gating .
Page 4 Contents RM0034 6.2.7 Clock security system (CSS) ....... . . 79 6.2.8 RTC clock .
Page 5 RM0034 Contents 7.3.4 APB2 peripheral reset register (RCC_APB2RSTR) ....119 7.3.5 APB1 peripheral reset register (RCC_APB1RSTR) ....120 7.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) .
Page 6 Contents RM0034 8.3.6 ADC alternate function remapping ......150 8.3.7 Timer alternate function remapping ......151 8.3.8 USART Alternate function remapping .
Page 7 RM0034 Contents 10.2 DMA main features ......... 175 10.3 DMA functional description .
Page 8 Contents RM0034 11.8 DMA request ..........202 11.9 Dual ADC mode .
Page 9 RM0034 Contents 12.3.3 DAC data format ......... 228 12.3.4 DAC conversion .
Page 10 Contents RM0034 12.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) ......... 243 12.5.12 DAC channel1 data output register (DAC_DOR1) .
Page 11 RM0034 Contents 13.4.6 Event generation register (TIMx_EGR) ......295 13.4.7 Capture/compare mode register 1 (TIMx_CCMR1) ....296 13.4.8 Capture/compare mode register 2 (TIMx_CCMR2) .
Page 12 Contents RM0034 14.4 TIMx registers ..........348 14.4.1 Control register 1 (TIMx_CR1) .
Page 13 RM0034 Contents 15.4.8 Auto-reload register (TIMx_ARR) ......378 15.4.9 TIM6&TIM7 register map ........379 Real-time clock (RTC) .
Page 14 Contents RM0034 18.1 WWDG introduction ........397 18.2 WWDG main features .
Page 15 RM0034 Contents Secure digital input/output interface (SDIO) ....449 20.1 SDIO main features ........449 20.2 SDIO bus topology .
Page 16 Contents RM0034 20.7.1 Command completion signal disable ......488 20.7.2 Command completion signal enable ......488 20.7.3 CE-ATA interrupt .
Page 17 RM0034 Contents 21.5.2 Endpoint-specific registers ........526 21.5.3 Buffer descriptor table .
Page 18 Contents RM0034 Serial peripheral interface (SPI) ......578 23.1 SPI introduction ......... . . 578 23.2 SPI and I S main features .
Page 19 RM0034 Contents 23.5.10 SPI register map ......... 616 Inter-integrated circuit (I C) interface .
Page 20 Contents RM0034 25.3.4 Fractional baud rate generation ......657 25.3.5 Multiprocessor communication ......659 25.3.6 Parity control .
Page 21 RM0034 Contents 26.6.2 OTG_FS global registers ........700 26.6.3 Host-mode registers .
Page 22 Contents RM0034 28.2.1 MAC core features ........815 28.2.2 DMA features .
Page 23 RM0034 Contents Device electronic signature ....... . . 924 29.1 Memory size registers .
Page 24 Contents RM0034 30.14.1 General description ........942 30.14.2 Timestamp packets, synchronization and overflow packets .
Page 25 RM0034 List of tables List of tables Table 1. Register boundary addresses ..........40 Table 2.
Page 26 List of tables RM0034 Table 50. Analog watchdog channel selection ......... 196 Table 51.
Page 27 RM0034 List of tables Table 102. Programmable NAND/PC Card access parameters ......436 Table 103.
Page 28 List of tables RM0034 Table 154. SPI interrupt requests ........... . 590 Table 155.
Page 29 RM0034 List of figures List of figures Figure 1. System architecture ............37 Figure 2.
Page 30 List of figures RM0034 Figure 49. DAC conversion (SW trigger enabled) with triangle wave generation ....233 Figure 50. Advanced-control timer block diagram ........248 Figure 51.
Page 31 RM0034 List of figures Figure 101. Counter timing diagram, internal clock divided by 1 ......317 Figure 102.
Page 32 List of figures RM0034 Figure 152. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)............. 373 Figure 153.
Page 33 RM0034 List of figures Figure 203. Filter bank scale configuration - register organization ......548 Figure 204.
Page 34 List of figures RM0034 Figure 255. Parity error detection using the 1.5 stop bits ........667 Figure 256.
Page 35 RM0034 List of figures Figure 307. Networked time synchronization ..........850 Figure 308.
Page 36: Documentation Conventions
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. Peripheral availability For peripheral availability and number across all STM32F10xxx sales types, please refer to the low-, medium- and high-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the connectivity line devices, STM32F105xx/STM32F107xx.
Page 37: Memory And Bus Architecture
RM0034 Memory and bus architecture Memory and bus architecture System architecture In low-, medium- and high-density devices, the main system consists of: ● Four masters: – Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) ●...
Page 38: Figure 2. System Architecture In Connectivity Line Devices
Memory and bus architecture RM0034 In connectivity line devices the main system consists of: ● Five masters: – Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) – Ethernet DMA ● Three slaves: – Internal SRAM –...
Page 39: Memory Organization
RM0034 Memory and bus architecture DCode bus This bus connects the DCode bus (literal load and debug access) of the Cortex™-M3 core to the Flash memory Data interface. System bus This bus connects the system bus of the Cortex™-M3 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA.
Page 40: Memory Map
Memory and bus architecture RM0034 Memory map See the datasheet corresponding to your device for a comprehensive diagram of the memory map. Table 1 gives the boundary addresses of the peripherals available in all STM32F10xxx devices. Table 1. Register boundary addresses Boundary address Peripheral Register map...
Page 41: Embedded Sram
RM0034 Memory and bus architecture Table 1. Register boundary addresses (continued) Boundary address Peripheral Register map 0x4000 7800 - 0x4000 FFFF Reserved 0x4000 7400 - 0x4000 77FF Section 12.5.14 on page 245 0x4000 7000 - 0x4000 73FF Power control PWR Section 4.4.3 on page 63 0x4000 6C00 - 0x4000 6FFF Backup registers (BKP)
Page 42: Bit Banding
Memory and bus architecture RM0034 2.3.2 Bit banding The Cortex™-M3 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.
Page 43: Table 2. Flash Module Organization (Low-Density Devices)
RM0034 Memory and bus architecture The Flash memory interface (FLITF) features: ● Read interface with prefetch buffer (2x64-bit words) ● Option byte Loader ● Flash Program / Erase operation ● Read / Write protection Table 2. Flash module organization (low-density devices) Block Name Base addresses...
Page 44: Table 3. Flash Module Organization (Medium-Density Devices)
Memory and bus architecture RM0034 Table 3. Flash module organization (medium-density devices) Block Name Base addresses Size (bytes) System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes Information block Option Bytes 0x1FFF F800 - 0x1FFF F80F FLASH_ACR 0x4002 2000 - 0x4002 2003 FLASH_KEYR 0x4002 2004 - 0x4002 2007 FLASH_OPTKEYR...
Page 45: Table 5. Flash Module Organization (Connectivity Line Devices)
RM0034 Memory and bus architecture Table 5. Flash module organization (connectivity line devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes Page 2 0x0800 1000 - 0x0800 17FF 2 Kbytes Page 3 0x0800 1800 - 0x0800 1FFF...
Page 46: Boot Configuration
Memory and bus architecture RM0034 Note: These options should be used in accordance with the Flash memory access time. The wait states represent the ratio of the SYSCLK (system clock) period to the Flash memory access time: ≤ zero wait state, if 0 < SYSCLK 24 MHz ≤...
Page 47 Embedded boot loader The embedded boot loader is used to reprogram the Flash memory using the USART1 serial interface. This program is located in the System memory and is programmed by ST during production. For further details please refer to AN2606.
Page 48: Crc Calculation Unit
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 49: Crc Functional Description
RM0034 CRC calculation unit CRC functional description The CRC calculation unit mainly consists of a single 32-bit data register, which: ● is used as an input register to enter new data in the CRC calculator (when writing into the register) ●...
Page 50: Independent Data Register (Crc_Idr)
CRC calculation unit RM0034 3.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 IDR[7:0] Reserved Bits 31:8 Reserved Bits 7:0 General-purpose 8-bit data register bits Can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.
Page 51: Power Control (Pwr)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 52: Independent A/D Converter Supply And Reference Voltage
Power control (PWR) RM0034 4.1.1 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB. ● The ADC voltage supply input is available on a separate V pin.
Page 53: Voltage Regulator
RM0034 Power control (PWR) Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 is restricted: only one I/O at a time can be used as an output, the speed has to be limited to 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g.
Page 54: Programmable Voltage Detector (Pvd)
Power control (PWR) RM0034 Figure 5. Power on reset/power down reset waveform 40 mV hysteresis Temporization RSTTEMPO Reset 4.2.2 Programmable voltage detector (PVD) You can use the PVD to monitor the V power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register (PWR_CR).
Page 55: Low-Power Modes
RM0034 Power control (PWR) Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several low- power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event.
Page 56: Peripheral Clock Gating
Power control (PWR) RM0034 4.3.2 Peripheral clock gating In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.
Page 57: Stop Mode
RM0034 Power control (PWR) Table 9. Sleep-now Sleep-now mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 and Mode entry – SLEEPONEXIT = 0 Refer to the Cortex™-M3 System Control register. If WFI was used for entry: Interrupt: Refer to Table 42: Vector table for other STM32F10xxx devices Mode exit...
Page 58: Standby Mode
Power control (PWR) RM0034 In Stop mode, the following features can be selected by programming individual control bits: ● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 17.3 Section 17: Independent watchdog (IWDG).
Page 59: Table 12. Standby Mode
RM0034 Power control (PWR) switched off. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry (see Figure Entering Standby mode Refer to Table 12 for more details on how to enter Standby mode. In Standby mode, the following features can be selected by programming individual control bits: ●...
Page 60: Auto-Wakeup (Awu) From Low-Power Mode
Power control (PWR) RM0034 Debug mode By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex™-M3 core is no longer clocked.
Page 61 RM0034 Power control (PWR) Bit 8 DBP: Disable backup domain write protection. In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and Backup registers disabled 1: Access to RTC and Backup registers enabled Bits 7:5 PLS[2:0]: PVD level selection.
Page 62: Power Control/Status Register (Pwr_Csr)
Power control (PWR) RM0034 4.4.2 Power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. Reserved Res. Reserved EWUP Reserved PVDO...
Page 63: Pwr Register Map
RM0034 Power control (PWR) 4.4.3 PWR register map The following table summarizes the PWR registers. Table 13. PWR - register map and reset values Offset Register PWR_CR PLS[2:0] 0x000 Reserved Reset value PWR_CSR 0x004 Reserved Reserved Reset value Refer to Table 1 on page 40 for the register boundary addresses.
Page 64: Backup Registers (Bkp)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 65: Bkp Functional Description
The clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits. For more details about RTC calibration and how to use it to improve timekeeping accuracy, please refer to AN2604 "STM32F101xx and STM32F103xx RTC calibration”. 65/959...
Page 66: Bkp Registers
Backup registers (BKP) RM0034 BKP registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. 5.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 0000 D[15:0] Bits 15:0 D[15:0] Backup data...
Page 67: Backup Control Register (Bkp_Cr)
RM0034 Backup registers (BKP) Bit 8 ASOE: Alarm or second output enable Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit. The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled while the ASOE bit is set.
Page 68: Backup Control/Status Register (Bkp_Csr)
Backup registers (BKP) RM0034 5.4.4 Backup control/status register (BKP_CSR) Address offset: 0x34 Reset value: 0x0000 0000 TPIE Reserved Reserved Bits 15:10 Reserved, always read as 0. Bit 9 TIF: Tamper interrupt flag This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is cleared by writing 1 to the CTI bit (also clears the interrupt).
Page 69: Bkp Register Map
RM0034 Backup registers (BKP) 5.4.5 BKP register map BKP registers are mapped as 16-bit addressable registers as described in the table below: Table 14. BKP register map and reset values Offset Register 0x00 Reserved BKP_DR1 D[15:0] 0x04 Reserved Reset value BKP_DR2 D[15:0] 0x08...
Page 70 Backup registers (BKP) RM0034 Table 14. BKP register map and reset values (continued) Offset Register BKP_DR12 D[15:0] 0x44 Reserved Reset value BKP_DR13 D[15:0] 0x48 Reserved Reset value BKP_DR14 D[15:0] 0x4C Reserved Reset value BKP_DR15 D[15:0] 0x50 Reserved Reset value BKP_DR16 D[15:0] 0x54 Reserved...
Page 71 RM0034 Backup registers (BKP) Table 14. BKP register map and reset values (continued) Offset Register 0x88 BKP_DR29 D[15:0] Reserved Reset value BKP_DR30 D[15:0] 0x8C Reserved Reset value BKP_DR31 D[15:0] 0x90 Reserved Reset value BKP_DR32 D[15:0] 0x94 Reserved Reset value BKP_DR33 D[15:0] 0x98 Reserved...
Page 72: Low-, Medium- And High-Density Reset And Clock Control (Rcc)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 73: Power Reset
RM0034 Low-, medium- and high-density reset and clock control (RCC) Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.
Page 74: Clocks
Low-, medium- and high-density reset and clock control (RCC) RM0034 Clocks Three different clock sources can be used to drive the system clock (SYSCLK): ● HSI oscillator clock ● HSE oscillator clock ● PLL clock The devices have the following two secondary clock sources: ●...
Page 75: Figure 8. Clock Tree
RM0034 Low-, medium- and high-density reset and clock control (RCC) Figure 8. Clock tree USBCLK 48 MHz to USB interface Prescaler /1, 1.5 I2S3CLK to I2S3 Peripheral clock I2S2CLK enable to I2S2 Peripheral clock SDIOCLK enable to SDIO 8 MHz Peripheral clock HSI RC enable...
Page 76: Hse Clock
Low-, medium- and high-density reset and clock control (RCC) RM0034 The timer clock frequencies are automatically fixed by hardware. There are two cases: if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected.
Page 77: Hsi Clock
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T =25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 78: Lse Clock
Low-, medium- and high-density reset and clock control (RCC) RM0034 If the USB interface is used in the application, the PLL must be programmed to output 48 or 72 MHz. This is needed to provide a 48 MHz USBCLK. 6.2.4 LSE clock The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator.
Page 79: System Clock (Sysclk) Selection
RM0034 Low-, medium- and high-density reset and clock control (RCC) Use the following procedure to calibrate the LSI: Enable TIM5 timer and configure channel4 in input capture mode Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purpose.
Page 80: Watchdog Clock
Low-, medium- and high-density reset and clock control (RCC) RM0034 The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: ● If LSE is selected as RTC clock: – The RTC continues to work even if the V supply is switched off, provided the supply is maintained.
Page 81: Clock Control Register (Rcc_Cr)
RM0034 Low-, medium- and high-density reset and clock control (RCC) 6.3.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access PLLON Reserved Reserved HSICAL[7:0] HSITRIM[4:0] HSION Res.
Page 82: Clock Configuration Register (Rcc_Cfgr)
Low-, medium- and high-density reset and clock control (RCC) RM0034 Bit 16 HSEON: External high-speed clock enable Set and cleared by software. Cleared by hardware to stop the external 1-25MHz oscillator when entering in Stop or Standby mode. This bit cannot be reset if the external 4-25 MHz oscillator is used directly or indirectly as the system clock or is selected to become the system clock.
Page 83 RM0034 Low-, medium- and high-density reset and clock control (RCC) Bits 26:24 MCO: Microcontroller clock output Set and cleared by software. 0xx: No clock 100: System clock (SYSCLK) selected 101: HSI clock selected 110: HSE clock selected 111: PLL clock divided by 2 selected Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.
Page 84 Low-, medium- and high-density reset and clock control (RCC) RM0034 Bits 14:14 ADCPRE: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADCs. 00: PLCK2 divided by 2 01: PLCK2 divided by 4 10: PLCK2 divided by 6 11: PLCK2 divided by 8 Bits 13:11 PPRE2: APB high-speed prescaler (APB2)
Page 85: Clock Interrupt Register (Rcc_Cir)
RM0034 Low-, medium- and high-density reset and clock control (RCC) Bits 1:0 SW: System clock switch Set and cleared by software to select SYSCLK source. Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled).
Page 86 Low-, medium- and high-density reset and clock control (RCC) RM0034 Bit 16 LSIRDYC: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0: No effect 1: LSIRDYF cleared Bits 15:13 Reserved, always read as 0. Bit 12 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock.
Page 87: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
RM0034 Low-, medium- and high-density reset and clock control (RCC) Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set. Cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the internal 8 MHz RC oscillator 1: Clock ready interrupt caused by the internal 8 MHz RC oscillator Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is...
Page 88 Low-, medium- and high-density reset and clock control (RCC) RM0034 Bit 12 SPI1RST: SPI 1 reset Set and cleared by software. 0: No effect 1: Reset SPI 1 Bit 11 TIM1RST: TIM1 timer reset Set and cleared by software. 0: No effect 1: Reset TIM1 timer Bit 10 ADC2RST: ADC 2 interface reset Set and cleared by software.
Page 89: Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)
RM0034 Low-, medium- and high-density reset and clock control (RCC) Bit 0 AFIORST: Alternate function I/O reset Set and cleared by software. 0: No effect 1: Reset Alternate Function 6.3.5 APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access UART UART...
Page 90 Low-, medium- and high-density reset and clock control (RCC) RM0034 Bit 22 I2C2RST: I2C 2 reset Set and cleared by software. 0: No effect 1: Reset I2C 2 Bit 21 I2C1RST: I2C 1 reset Set and cleared by software. 0: No effect 1: Reset I2C 1 Bit 20 UART5RST: USART 5 reset Set and cleared by software.
Page 91: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
RM0034 Low-, medium- and high-density reset and clock control (RCC) Bit 4 TIM6RST: Timer 6 reset Set and cleared by software. 0: No effect 1: Reset timer 6 Bit 3 TIM5RST: Timer 5 reset Set and cleared by software. 0: No effect 1: Reset timer 5 Bit 2 TIM4RST: Timer 4 reset Set and cleared by software.
Page 92 Low-, medium- and high-density reset and clock control (RCC) RM0034 Bit 8 FSMCEN: FSMC clock enable Set and cleared by software. 0: FSMC clock disabled 1: FSMC clock enabled Bit 7 Reserved, always read as 0. Bit 6 CRCEN: CRC clock enable Set and cleared by software.
Page 93: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
RM0034 Low-, medium- and high-density reset and clock control (RCC) 6.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x18 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going.
Page 94 Low-, medium- and high-density reset and clock control (RCC) RM0034 Bit 9 ADC1EN: ADC 1 interface clock enable Set and cleared by software. 0: ADC 1 interface disabled 1: ADC 1 interface clock enabled Bit 8 IOPGEN: I/O port G clock enable Set and cleared by software.
Page 95: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
RM0034 Low-, medium- and high-density reset and clock control (RCC) 6.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going.
Page 96 Low-, medium- and high-density reset and clock control (RCC) RM0034 Bit 22 I2C2EN: I2C 2 clock enable Set and cleared by software. 0: I2C 2 clock disabled 1: I2C 2 clock enabled Bit 21 I2C1EN: I2C 1 clock enable Set and cleared by software. 0: I2C 1 clock disabled 1: I2C 1 clock enabled Bit 20 UART5EN: USART 5 clock enable...
Page 97: Backup Domain Control Register (Rcc_Bdcr)
RM0034 Low-, medium- and high-density reset and clock control (RCC) Bit 4 TIM6EN: Timer 6 clock enable Set and cleared by software. 0: Timer 6 clock disabled 1: Timer 6 clock enabled Bit 3 TIM5EN: Timer 5 clock enable Set and cleared by software. 0: Timer 5 clock disabled 1: Timer 5 clock enabled Bit 2 TIM4EN: Timer 4 clock enable...
Page 98 Low-, medium- and high-density reset and clock control (RCC) RM0034 Bit 15 RTCEN: RTC clock enable Set and cleared by software. 0: RTC clock disabled 1: RTC clock enabled Bits 14:10 Reserved, always read as 0. Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC.
Page 99: Control/Status Register (Rcc_Csr)
RM0034 Low-, medium- and high-density reset and clock control (RCC) 6.3.10 Control/status register (RCC_CSR) Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register.
Page 100: Rcc Register Map
Low-, medium- and high-density reset and clock control (RCC) RM0034 Bit 25 Reserved, always read as 0. Bit 24 RMVF: Remove reset flag Set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 23:2 Reserved, always read as 0.
Page 101 RM0034 Low-, medium- and high-density reset and clock control (RCC) Table 15. RCC - register map and reset values (continued) Offset Register 0x018 RCC_APB2ENR Reserved Reset value RCC_APB1ENR 0x01C Reserved Reset value RCC_BDCR 0x020 Reserved Reserved Reserved [1:0] Reset value RCC_CSR 0x024 Reserved...
Page 102: Connectivity Line Devices: Reset And Clock Control (Rcc)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 103: Power Reset
RM0034 Connectivity line devices: reset and clock control (RCC) Low-power management reset There are two ways to generate a low-power management reset: Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.
Page 104: Clocks
Connectivity line devices: reset and clock control (RCC) RM0034 Clocks Three different clock sources can be used to drive the system clock (SYSCLK): ● HSI oscillator clock ● HSE oscillator clock ● PLL1 clock The devices have the following two secondary clock sources: ●...
Page 105: Figure 11. Clock Tree
RM0034 Connectivity line devices: reset and clock control (RCC) Figure 11. Clock tree 40 kHz to independent watchdog IWDGCLK OSC32_IN to RTC 32.768 kHz RTCCLK OSC32_OUT /128 RTCSEL[1:0] to Flash prog. IF FLITFCLK XT1 to MCO 8 MHz SYSCLK HSI RC PLL1MUL system clock 3-25 MHz...
Page 106: Hse Clock
Connectivity line devices: reset and clock control (RCC) RM0034 the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is 36 MHz. All peripheral clocks are derived from the system clock (SYSCLK) except: ● The Flash memory programming interface clock which is always the HSI clock ●...
Page 107: Hsi Clock
RM0034 Connectivity line devices: reset and clock control (RCC) Figure 12. HSE/ LSE clock sources Hardware configuration OSC_OUT External clock (HiZ) EXTERNAL SOURCE OSC_IN OSC_OUT Crystal/ceramic resonators LOAD CAPACITORS External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 50 MHz.
Page 108: Plls
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T = 25 °C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 109: Lsi Clock
RM0034 Connectivity line devices: reset and clock control (RCC) External source (LSE bypass) In this mode, an external clock source must be provided. It must have a frequency of 32.768 kHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register (RCC_BDCR).
Page 110: Clock Security System (Css)
Connectivity line devices: reset and clock control (RCC) RM0034 7.2.7 Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled, a clock failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is generated to inform the software about the failure (Clock Security System...
Page 111: Clock-Out Capability
RM0034 Connectivity line devices: reset and clock control (RCC) 7.2.10 Clock-out capability The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 8 clock signals can be selected as the MCO clock.
Page 112 Connectivity line devices: reset and clock control (RCC) RM0034 Bit 28 PLL3ON: PLL3 enable Set and cleared by software to enable PLL3. Cleared by hardware when entering Stop or Standby mode. 0: PLL3 OFF 1: PLL3 ON Bit 27 PLL2RDY: PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked.
Page 113: Clock Configuration Register (Rcc_Cfgr)
RM0034 Connectivity line devices: reset and clock control (RCC) Bit 16 HSEON: External high-speed clock enable Set and cleared by software. Cleared by hardware to stop the external 3-25MHz oscillator when entering Stop or Standby mode. This bit can not be reset if the external 3-25 MHz oscillator is used directly or indirectly as system clock or is selected to become the system clock.
Page 114 Connectivity line devices: reset and clock control (RCC) RM0034 Bits 26:24 MCO[3:0]: Microcontroller clock output Set and cleared by software. 00xx: No clock 0100: System clock (SYSCLK) selected 0101: HSI clock selected 0110: HSE clock selected 0111: PLL1 clock divided by 2 selected 1000: PLL2 clock selected 1001: PLL3 clock divided by 2 selected 1010: XT1 external 3-25 MHz oscillator clock selected (for Ethernet)
Page 115 RM0034 Connectivity line devices: reset and clock control (RCC) Bits 14:14 ADCPRE[1:0]: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADCs. 00: PLCK2 divided by 2 01: PLCK2 divided by 4 10: PLCK2 divided by 6 11: PLCK2 divided by 8 Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2) Set and cleared by software to control the division factor of the APB High speed clock (PCLK2).
Page 116: Clock Interrupt Register (Rcc_Cir)
Connectivity line devices: reset and clock control (RCC) RM0034 Bits 1:0 SW[1:0]: System clock Switch Set and cleared by software to select SYSCLK source. Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled).
Page 117 RM0034 Connectivity line devices: reset and clock control (RCC) Bit 18 HSIRDYC: HSI ready interrupt clear This bit is set by software to clear the HSIRDYF flag. 0: No effect 1: Clear HSIRDYF flag Bit 17 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag.
Page 118 Connectivity line devices: reset and clock control (RCC) RM0034 Bit 7 CSSF: Clock security system interrupt flag Set by hardware when a failure is detected in the external 3-25 MHz oscillator. It is cleared by software setting the CSSC bit. 0: No clock security interrupt caused by HSE clock failure 1: Clock security interrupt caused by HSE clock failure Bit 6 PLL3RDYF: PLL3 Ready Interrupt flag...
Page 119: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
RM0034 Connectivity line devices: reset and clock control (RCC) 7.3.4 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x0C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access Reserved USART1 SPI1 TIM1 ADC2 ADC1 IOPE IOPD IOPC IOPB IOPA AFIO...
Page 120: Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)
Connectivity line devices: reset and clock control (RCC) RM0034 Bit 4 IOPCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset I/O port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset I/O port B Bit 2 IOPARST: I/O port A reset...
Page 121 RM0034 Connectivity line devices: reset and clock control (RCC) Bit 27 BKPRST: Backup interface reset Set and cleared by software. 0: No effect 1: Reset backup interface Bit 26 CAN2RST: CAN2 reset Set and cleared by software. 0: No effect 1: Reset CAN2 Bit 25 CAN1RST: CAN1 reset Set and cleared by software.
Page 122 Connectivity line devices: reset and clock control (RCC) RM0034 Bits 13:12 Reserved, always read as 0. Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: No effect 1: Reset window watchdog Bits 10:6 Reserved, always read as 0. Bit 5 TIM7RST: Timer 7 reset Set and cleared by software.
Page 123: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
RM0034 Connectivity line devices: reset and clock control (RCC) 7.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) Address offset: 0x14 Reset value: 0x0000 0014 Access: no wait state, word, half-word and byte access MACR Reserved ETHM SRAM DMA2 DMA1 ETHM OTGF FLITFE ACTX CRCEN...
Page 124: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
Connectivity line devices: reset and clock control (RCC) RM0034 Bit 4 FLITFEN: FLITF clock enable Set and cleared by software to disable/enable FLITF clock during sleep mode. 0: FLITF clock disabled during Sleep mode 1: FLITF clock enabled during Sleep mode Bit 3 Reserved, always read as 0.
Page 125 RM0034 Connectivity line devices: reset and clock control (RCC) Bit 11 TIM1EN: TIM1 Timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1 timer clock enabled Bit 10 ADC2EN: ADC 2 interface clock enable Set and cleared by software. 0: ADC 2 interface clock disabled 1: ADC 2 interface clock enabled Bit 9 ADC1EN: ADC 1 interface clock enable...
Page 126: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
Connectivity line devices: reset and clock control (RCC) RM0034 7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going.
Page 127 RM0034 Connectivity line devices: reset and clock control (RCC) Bit 21 I2C1EN: I2C 1 clock enable Set and cleared by software. 0: I2C 1 clock disabled 1: I2C 1 clock enabled Bit 20 UART5EN: USART 5 clock enable Set and cleared by software. 0: USART 5 clock disabled 1: USART 5 clock enabled Bit 19 UART4EN: USART 4 clock enable...
Page 128 Connectivity line devices: reset and clock control (RCC) RM0034 Bit 3 TIM5EN: Timer 5 clock enable Set and cleared by software. 0: Timer 5 clock disabled 1: Timer 5 clock enabled Bit 2 TIM4EN: Timer 4 clock enable Set and cleared by software. 0: Timer 4 clock disabled 1: Timer 4 clock enabled Bit 1 TIM3EN: Timer 3 clock enable...
Page 129: Backup Domain Control Register (Rcc_Bdcr)
RM0034 Connectivity line devices: reset and clock control (RCC) 7.3.9 Backup domain control register (RCC_BDCR) Address: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in the case of successive accesses to this register. Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register...
Page 130: Control/Status Register (Rcc_Csr)
Connectivity line devices: reset and clock control (RCC) RM0034 Bit 1 LSERDY: External Low Speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low speed oscillator clock cycles 0: External 32 kHz oscillator not ready 1: External 32 kHz oscillator ready...
Page 131 RM0034 Connectivity line devices: reset and clock control (RCC) Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs. It is cleared by writing to the RMVF bit. 0: No POR/PDR reset occurred 1: POR/PDR reset occurred Bit 26 PINRSTF: PIN reset flag Set by hardware when a reset from the NRST pin occurs.
Page 132: Ahb Peripheral Clock Reset Register (Rcc_Ahbrstr)
Connectivity line devices: reset and clock control (RCC) RM0034 7.3.11 AHB Peripheral Clock reset register (RCC_AHBRSTR) Address offset: 0x28 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Reserved ETHMAC OTGFS Res. Res. Reserved Bits 31:15 Reserved, always read as 0. Bit 14 ETHMACRST Ethernet MAC reset Set and cleared by software.
Page 133: Clock Configuration Register2 (Rcc_Cfgr2)
RM0034 Connectivity line devices: reset and clock control (RCC) 7.3.12 Clock configuration register2 (RCC_CFGR2) Address offset: 0x2C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access I2S3S I2S2S PREDI V1SRC Reserved PLL3MUL[3:0] PLL2MUL[3:0] PREDIV2[3:0] PREDIV1[3:0] Bits 31:19 Reserved, always read as 0. Bit 18 I2S3SRC: I2S3 clock source Set and cleared by software to select I2S3 clock source.
Page 134 Connectivity line devices: reset and clock control (RCC) RM0034 Bits 11:8 PLL2MUL[3:0]: PLL2 Multiplication Factor Set and cleared by software to control PLL2 multiplication factor. These bits can be written only when PLL2 is disabled. 00xx: Reserved 010x: Reserved 0110: PLL2 clock entry x 8 0111: PLL2 clock entry x 9 1000: PLL2 clock entry x 10 1001: PLL2 clock entry x 11...
Page 135: Rcc Register Map
RM0034 Connectivity line devices: reset and clock control (RCC) Bits 3:0 PREDIV1[3:0]: PREDIV1 division factor Set and cleared by software to select PREDIV1 division factor. These bits can be written only when PLL1 is disabled. Note: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the RCC_CFGR register changes Bit(0) accordingly.
Page 136 Connectivity line devices: reset and clock control (RCC) RM0034 Table 16. RCC register map and reset values (continued) Offset Register RCC_AHBENR 0x014 Reserved Reserved Reset value 0x018 RCC_APB2ENR Reserved Reset value RCC_APB1ENR Reser 0x01C Reserved Reset value RCC_BDCR 0x020 Reserved Reserved Reserved [1:0]...
Page 137: General-Purpose And Alternate-Function I/Os (Gpios And Afios)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 138: Figure 13. Basic Structure Of A Standard I/O Port Bit
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0034 Figure 13. Basic structure of a standard I/O port bit Analog Input To on-chip peripheral on/off Alternate Function Input on/off Read TTL Schmitt Protection trigger on/off diode Input driver I/O pin Write Output driver Protection diode...
Page 139: General-Purpose I/O (Gpio)
RM0034 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 17. Port bit configuration table PxODR Configuration mode CNF1 CNF0 MODE1 MODE0 register Push-pull 0 or 1 General purpose output Open-drain 0 or 1 Push-pull don’t care Alternate Function Table 18 output Open-drain don’t care...
Page 140: External Interrupt/Wakeup Lines
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0034 8.1.3 External interrupt/wakeup lines All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode. For more information on external interrupts, refer to: ● Section 9.2: External interrupt/event controller (EXTI) on page 167 ●...
Page 141: Input Configuration
RM0034 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.1.7 Input configuration When the I/O Port is programmed as Input: ● The Output Buffer is disabled ● The Schmitt Trigger Input is activated ● The weak pull-up and pull-down resistors are activated or not depending on input configuration (pull-up, pull-down or floating): ●...
Page 142: Alternate Function Configuration
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0034 Figure 16. Output configuration Read or V DD_FT TTL Schmitt Protection trigger diode Write Input driver I/O pin Output driver Protection diode P-MOS Output control Read/write N-MOS Push-pull or Open-drain ai14784 1. V is a potential specific to five-volt tolerant I/Os and different from V DD_FT 8.1.9...
Page 143: Analog Input Configuration
RM0034 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 17. Alternate function configuration Alternate Function Input To on-chip peripheral Read or V DD_FT TTL Schmitt Protection trigger diode Input driver I/O pin Write Output driver Protection diode P-MOS Output control N-MOS Read/write push-pull or...
Page 144: Gpio Registers
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0034 GPIO registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. 8.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) Address offset: 0x00 Reset value: 0x4444 4444 CNF7[1:0] MODE7[1:0] CNF6[1:0]...
Page 145: Port Configuration Register High (Gpiox_Crh) (X=A..g
RM0034 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) Address offset: 0x04 Reset value: 0x4444 4444 CNF15[1:0] MODE15[1:0] CNF14[1:0] MODE14[1:0] CNF13[1:0] MODE13[1:0] CNF12[1:0] MODE12[1:0] CNF11[1:0] MODE11[1:0] CNF10[1:0] MODE10[1:0] CNF9[1:0] MODE9[1:0] CNF8[1:0] MODE8[1:0] Bits 31:30, 27:26, CNFy[1:0]: Port x configuration bits (y= 8 ..
Page 146: Port Output Data Register (Gpiox_Odr) (X=A
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0034 8.2.4 Port output data register (GPIOx_ODR) (x=A..G) Address offset: 0x0C Reset value: 0x0000 0000 Reserved ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 Bits 31:16 Reserved, always read as 0.
Page 147: Port Bit Reset Register (Gpiox_Brr) (X=A..g
RM0034 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) Address offset: 0x14 Reset value: 0x0000 0000 Reserved BR15 BR14 BR13 BR12 BR11 BR10 Bits 31:16 Reserved Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only.
Page 148: Alternate Function I/O And Debug Configuration (Afio)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0034 Bit 16 LCKK[16]: Lock key This bit can be read anytime. It can only be modified using the Lock Key Writing Sequence. 0: Port configuration lock key not active 1: Port configuration lock key active. GPIOx_LCKR register is locked until an MCU reset occurs.
Page 149: Can1 Alternate Function Remapping
RM0034 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.3.3 CAN1 alternate function remapping The CAN signals can be mapped on Port A, Port B or Port D as shown in Table 19. For port D, remapping is not possible in devices delivered in 36-, 48- and 64-pin packages. Table 19.
Page 150: Adc Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0034 Table 22. Debug port mapping SWJ I/O pin assigned PB3 / SWJ _CFG PA13 / PA14 / Available debug ports PA15 / JTDO/ PB4/ [2:0] JTMS/ JTCK/S JTDI TRACE JNTRST SWDIO WCLK Full SWJ (JTAG-DP + SW-DP) (Reset state) Full SWJ (JTAG-DP + SW-DP)
Page 151: Timer Alternate Function Remapping
RM0034 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 26. ADC2 external trigger regular conversion alternate function remapping Alternate function ADC2_ETRGREG_REG = 0 ADC2_ETRGREG_REG = 1 ADC2 external trigger regular ADC2 external trigger regular ADC2 external trigger regular conversion is connected to conversion is connected to conversion EXTI11...
Page 152: Usart Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0034 Table 30. Timer 2 alternate function remapping TIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1: Alternate function 0] = “00” (no 0] = “01” (partial 0] = “10” (partial 0] = “11” (full remap) remap) remap) remap) TIM2_CH1_ETR PA15...
Page 153: I2C 1 Alternate Function Remapping
RM0034 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 33. USART2 remapping Alternate functions USART2_REMAP = 0 USART2_REMAP = 1 USART2_CTS USART2_RTS USART2_TX USART2_RX USART2_CK 1. Remap available only for 100-pin and 144-pin packages. Table 34. USART1 remapping Alternate function USART1_REMAP = 0 USART1_REMAP = 1 USART1_TX...
Page 154: Ethernet Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0034 Table 37. SPI3 remapping Alternate function SPI3_REMAP = 0 SPI3_REMAP = 1 SPI1_NSS PA15 SPI1_SCK PC10 SPI1_MISO PC11 SPI1_MOSI PC12 8.3.12 Ethernet alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR).
Page 155: Af Remap And Debug I/O Configuration Register (Afio_Mapr)
RM0034 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 6:4 PORT[2:0]: Port selection Set and cleared by software. Select the port used to output the Cortex EVENTOUT signal. Note: The EVENTOUT signal output capability is not extended to ports PF and PG. 000: PA selected 001: PB selected 010: PC selected...
Page 156 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0034 Bit 28 SPI3_REMAP SPI3 remapping This bit is set and cleared by software. It controls the mapping of SPI3 NSS, SCK, MISO, MOSI alternate functions on the GPIO ports. 0: No remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) 1: Remap (NSS/PA4, SCK/PC10, MISO/PC11, MOSI/PC12) Note: This bit is available only in connectivity line devices and is reserved otherwise.
Page 157 RM0034 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 14:13 CAN1_REMAP[1:0]: CAN1 alternate function remapping These bits are set and cleared by software. They control the mapping of Alternate Functions CAN1_RX and CAN1_TX in connectivity line devices, and CAN_RX and CAN_TX in other devices with a single CAN interface.
Page 158: External Interrupt Configuration Register 1 (Afio_Exticr1)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0034 Bit 3 USART2_REMAP USART2 remapping This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) 1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) Bit 2 USART1_REMAP USART1 remapping This bit is set and cleared by software.
Page 159: External Interrupt Configuration Register 2 (Afio_Exticr2)
RM0034 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 8.4.4 External interrupt configuration register 2 (AFIO_EXTICR2) Address offset: 0x0C Reset value: 0x0000 Reserved EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 4 to 7) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 160: External Interrupt Configuration Register 4 (Afio_Exticr4)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0034 8.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) Address offset: 0x14 Reset value: 0x0000 Reserved EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 12 to 15) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 161: Table 40. Afio Register Map And Reset Values
RM0034 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 40. AFIO register map and reset values Offset Register AFIO_EVCR PORT[2:0] PIN[3:0] 0x00 Reserved Reset value AFIO_MAPR 0x04 Reset value AFIO_EXTICR1 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] 0x08 Reserved Reset value AFIO_EXTICR2 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]...
Page 162: Interrupts And Events
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 163: Table 41. Vector Table For Connectivity Line Devices
RM0034 Interrupts and events Table 41. Vector table for connectivity line devices (continued) Type of Acronym Description Address priority fixed HardFault All class of fault 0x0000_000C settable MemManage Memory management 0x0000_0010 settable BusFault Pre-fetch fault, memory access fault 0x0000_0014 settable UsageFault Undefined instruction or illegal state 0x0000_0018...
Page 164 Interrupts and events RM0034 Table 41. Vector table for connectivity line devices (continued) Type of Acronym Description Address priority settable CAN1_SCE CAN1 SCE interrupt 0x0000_0098 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000_009C settable TIM1_BRK TIM1 Break interrupt 0x0000_00A0 settable TIM1_UP TIM1 Update interrupt 0x0000_00A4 TIM1 Trigger and Commutation settable...
Page 165: Table 42. Vector Table For Other Stm32F10Xxx Devices
RM0034 Interrupts and events Table 41. Vector table for connectivity line devices (continued) Type of Acronym Description Address priority settable DMA2_Channel4 DMA2 Channel4 global interrupt 0x0000_012C settable DMA2_Channel5 DMA2 Channel5 global interrupt 0x0000_0130 settable Ethernet global interrupt 0x0000_0134 Ethernet Wakeup through EXTI line settable ETH_WKUP 0x0000_0138...
Page 166 Interrupts and events RM0034 Table 42. Vector table for other STM32F10xxx devices (continued) Type of Acronym Description Address priority settable FLASH Flash global interrupt 0x0000_0050 settable RCC global interrupt 0x0000_0054 settable EXTI0 EXTI Line0 interrupt 0x0000_0058 settable EXTI1 EXTI Line1 interrupt 0x0000_005C settable EXTI2...
Page 167: External Interrupt/Event Controller (Exti)
RM0034 Interrupts and events Table 42. Vector table for other STM32F10xxx devices (continued) Type of Acronym Description Address priority settable SPI2 SPI2 global interrupt 0x0000_00D0 settable USART1 USART1 global interrupt 0x0000_00D4 settable USART2 USART2 global interrupt 0x0000_00D8 settable USART3 USART3 global interrupt 0x0000_00DC settable EXTI15_10...
Page 168: Main Features
Interrupts and events RM0034 9.2.1 Main features The EXTI controller main features are the following: ● Independent trigger and mask on each interrupt/event line ● Dedicated status bit for each interrupt line ● Generation of up to 20 software event/interrupt requests ●...
Page 169: Functional Description
RM0034 Interrupts and events In connectivity line devices, Ethernet wakeup events also have the WFE wakeup capability. To use an external line as a wakeup event, refer to Section 9.2.4: Functional description. 9.2.4 Functional description To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’...
Page 170: Figure 20. External Interrupt/Event Gpio Mapping
Interrupts and events RM0034 Figure 20. External interrupt/event GPIO mapping EXTI0[3:0] bits in AFIO_EXTICR1 register EXTI0 EXTI1[3:0] bits in AFIO_EXTICR1 register EXTI1 EXTI15[3:0] bits in AFIO_EXTICR4 register PA15 PB15 PC15 EXTI15 PD15 PE15 PF15 PG15 The four other EXTI lines are connected as follows: ●...
Page 171: Exti Registers
RM0034 Interrupts and events registers EXTI Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. 9.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 MR19 MR18 MR17 MR16 Reserved MR15 MR14 MR13 MR12...
Page 172: Rising Trigger Selection Register (Exti_Rtsr)
Interrupts and events RM0034 9.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 TR19 TR18 TR17 TR16 Reserved TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line.
Page 173: Software Interrupt Event Register (Exti_Swier)
RM0034 Interrupts and events 9.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 SWIER SWIER SWIER SWIER Reserved SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER Bits 31:20 Reserved, must be kept at reset value (0).
Page 174: Exti Register Map
Interrupts and events RM0034 9.3.7 EXTI register map The following table gives the EXTI register map and the reset values. B in all registers, it 19 used in connectivity line devices and is reserved otherwise. Table 43. External interrupt/event controller register map and reset values Offset Register EXTI_IMR...
Page 175: Dma Controller (Dma)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 176: Dma Functional Description
DMA controller (DMA) RM0034 Figure 21. DMA block diagram in connectivity line devices ICode Flash FLITF DCode Cortex-M3 Sys tem SRAM DMA1 Ch.1 Reset & clock Ch.2 control (RCC) Bridge 2 Ch.7 APB2 Bridge 1 APB1 Arbiter SPI3/I2S ADC1 GPIOC DMA request ADC2 SPI2/I2S...
Page 177: Arbiter
RM0034 DMA controller (DMA) release the Acknowledge. If there are more requests, the peripheral can initiate the next transaction. In summary, each DMA transfer consists of three operations: ● A load from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register.
Page 178 DMA controller (DMA) RM0034 transfer operations, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in noncircular mode, no DMA requests are served after the last transfer (i.e.
Page 179: Programmable Data Width, Data Alignment And Endians
RM0034 DMA controller (DMA) 10.3.4 Programmable data width, data alignment and endians When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 44: Programmable data width & endian behavior (when bits PINC = MINC = Table 44.
Page 180: Error Management
DMA controller (DMA) RM0034 and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below: ● To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord ●...
Page 181: Figure 22. Dma1 Request Mapping
RM0034 DMA controller (DMA) The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral. Figure 22. DMA1 request mapping Fixed hardware priority Peripheral request signals High priority ADC1 HW request 1 Channel 1 TIM2_CH3 TIM4_CH1...
Page 182: Table 46. Summary Of Dma1 Requests For Each Channel
DMA controller (DMA) RM0034 Table 46. Summary of DMA1 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ADC1 ADC1 SPI/I SPI1_RX SPI1_TX SPI/I2S2_RX SPI/I2S2_TX USART USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX I2C2_TX I2C2_RX I2C1_TX...
Page 183: Table 47. Summary Of Dma2 Requests For Each Channel
RM0034 DMA controller (DMA) Figure 23. DMA2 request mapping Peripheral request signals Fixed hardware priority TIM5_CH4 HIGH PRIORITY TIM5_TRIG HW request 1 Channel 1 TIM8_CH3 TIM8_UP SW trigger (MEM2MEM bit) SPI/I2S3_RX Channel 1 EN bit TIM8_CH4 HW request 2 TIM8_TRIG Channel 2 TIM8_COM TIM5_CH3...
Page 184: Dma Registers
DMA controller (DMA) RM0034 10.4 DMA registers Refer to Section 1.1 on page 36 for a list of abbreviations used in the register descriptions. Note: In the following registers, all bits relative to channel6 and channel7 are not relevant for DMA2 since it has only 5 channels.
Page 185: Dma Interrupt Flag Clear Register (Dma
RM0034 DMA controller (DMA) 10.4.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF Reserved CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF...
Page 186: Dma Channel X Configuration Register (Dma_Ccrx) (X = 1
DMA controller (DMA) RM0034 10.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1 ..7) Address offset: 0x08 + 20d × Channel number Reset value: 0x0000 0000 Reserved MEM2 PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC TEIE HTIE TCIE Res. Bits 31:15 Reserved, always read as 0.
Page 187: Dma Channel X Number Of Data Register (Dma_Cndtrx) (X = 1
RM0034 DMA controller (DMA) Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 2 HTIE: Half transfer interrupt enable...
Page 188: Dma Channel X Peripheral Address Register (Dma_Cparx) (X = 1
DMA controller (DMA) RM0034 10.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1 ..7) Address offset: 0x10 + dx20 × Channel number Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written.
Page 189: Dma Register Map
RM0034 DMA controller (DMA) 10.4.7 DMA register map The following table gives the DMA register map and the reset values. Table 48. DMA register map and reset values Offset Register DMA_ISR Reserved 0x000 Reset value DMA_IFCR 0x004 Reserved Reset value PSIZ DMA_CCR1 SIZE...
Page 190 DMA controller (DMA) RM0034 Table 48. DMA register map and reset values (continued) Offset Register DMA_CPAR4 PA[31:0] 0x04C Reset value DMA_CMAR4 MA[31:0] 0x050 Reset value 0x054 Reserved PSIZ DMA_CCR5 SIZE [1:0] 0x058 Reserved [1:0] [1:0] Reset value DMA_CNDTR5 NDT[15:0] 0x05C Reserved Reset value DMA_CPAR5...
Page 191: Analog-To-Digital Converter (Adc)
STM32F103xx performance line devices: 1 µs at 56 MHz (1.17 µs at 72 MHz) – STM32F101xx access line devices: 1 µs at 28 MHz (1.55 µs at 36 MHz) – STM32F102xx USB access line devices: 1.2 µs at 48 MHz –...
Page 192: Adc Functional Description
Analog-to-digital converter (ADC) RM0034 The block diagram of the ADC is shown in Figure Note: ,if available (depending on package), must be tied to V REF- 11.3 ADC functional description Figure 24 shows a single ADC block diagrams and Table 49 gives the ADC pin description.
Page 193: Figure 24. Single Adc Block Diagram
RM0034 Analog-to-digital converter (ADC) Figure 24. Single ADC block diagram Interrupt Flags enable bits End of conversion EOCIE ADC Interrupt to NVIC End of injected conversion JEOC JEOCIE Analog watchdog event AWDIE Analog watchdog Compare Result High Threshold (12 bits) Low Threshold (12 bits) Injected data registers REF+...
Page 194: Adc On-Off Control
Analog-to-digital converter (ADC) RM0034 Table 49. ADC pins Name Signal type Remarks The higher/positive reference voltage for the ADC, Input, analog reference ≤ ≤ REF+ positive 2.4 V REF+ Analog power supply equal to V Input, analog supply ≤ ≤ 2.4 V (3.6 V) Input, analog reference...
Page 195: Single Conversion Mode
RM0034 Analog-to-digital converter (ADC) Temperature sensor/V internal channels REFINT The Temperature sensor is connected to channel ADCx_IN16 and the internal reference voltage V is connected to ADCx_IN17. These two internal channels can be selected REFINT and converted as injected or regular channels. Note: The sensor and V are only available on the master ADC1 peripheral.
Page 196: Analog Watchdog
Analog-to-digital converter (ADC) RM0034 Figure 25. Timing diagram ADC_CLK SET ADON Start 1st conversion Start next conversion ADC power on ADC Conversion Next ADC Conversion STAB Conversion Time (total conv time) Software resets EOC bit 11.3.7 Analog watchdog The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold.
Page 197: Scan Mode
RM0034 Analog-to-digital converter (ADC) 11.3.8 Scan mode This mode is used to scan a group of analog channels. Scan mode can be selected by setting the SCAN bit in the ADC_CR1 register. Once this bit is set, ADC scans all the channels selected in the ADC_SQRx registers (for regular channels) or in the ADC_JSQR (for injected channels).
Page 198: Discontinuous Mode
Figure 27. Injected conversion latency ADC clock Inj. event Reset ADC max latency 1. The maximum latency value can be found in the electrical characteristics of the STM32F101xx and STM32F103xx datasheets. 11.3.10 Discontinuous mode Regular group This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n <=8) which is a part of the sequence of...
Page 199: Calibration
RM0034 Analog-to-digital converter (ADC) Example: n = 1, channels to be converted = 1, 2, 3 1st trigger: channel 1 converted 2nd trigger: channel 2 converted 3rd trigger: channel 3 converted and EOC and JEOC events generated 4th trigger: channel 1 Note: When all injected channels are converted, the next trigger starts the conversion of the first injected channel.
Page 200: Channel-By-Channel Programmable Sample Time
Analog-to-digital converter (ADC) RM0034 Figure 29. Right alignment of data Injected group SEXT SEXT SEXT SEXT Regular group Figure 30. Left alignment of data Injected group SEXT Regular group 11.6 Channel-by-channel programmable sample time ADC samples the input voltage for a number of ADC_CLK cycles which can be modified us- ing the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers.
Page 201: Table 51. External Trigger For Regular Channels For Adc1 And Adc2
RM0034 Analog-to-digital converter (ADC) Table 51. External trigger for regular channels for ADC1 and ADC2 Source Type EXTSEL[2:0] TIM1_CC1 event TIM1_CC2 event TIM1_CC3 event Internal signal from on-chip timers TIM2_CC2 event TIM3_TRGO event TIM4_CC4 event EXTI line11/TIM8_TRGO External pin/Internal signal from (1)(2) event on-chip timers...
Page 202: Dma Request
Analog-to-digital converter (ADC) RM0034 Table 53. External trigger for regular channels for ADC3 Source Connection type EXTSEL[2:0] TIM3_CC1 event TIM2_CC3 event TIM1_CC3 event Internal signal from on-chip TIM8_CC1 event timers TIM8_TRGO event TIM5_CC1 event TIM5_CC3 event SWSTART Software control bit Table 54.
Page 203: Dual Adc Mode
RM0034 Analog-to-digital converter (ADC) 11.9 Dual ADC mode In devices with two ADCs or more, dual ADC mode can be used (see Figure 31). In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0] bits in the ADC1_CR1 register.
Page 204: Figure 31. Dual Adc Block Diagram
Analog-to-digital converter (ADC) RM0034 Figure 31. Dual ADC block diagram Regular data register (12 bits) (16 bits) Injected data registers (4 x 16 bits) Regular ADC2 (Slave) channels injected channels internal triggers Regular data register (16 bits)* Injected data registers (4 x 16 bits) ADCx_IN0 Regular...
Page 205: Injected Simultaneous Mode
RM0034 Analog-to-digital converter (ADC) 11.9.1 Injected simultaneous mode This mode converts an injected channel group. The source of external trigger comes from the injected group mux of ADC1 (selected by the JEXTSEL[2:0] bits ADC1_CR2 in the register). A simultaneous trigger is provided to ADC2. Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel).
Page 206: Fast Interleaved Mode
Analog-to-digital converter (ADC) RM0034 Figure 33. Regular simultaneous mode on 16 channels Sampling Conversion ADC1 CH15 ADC2 CH15 CH14 CH13 CH12 End of conversion on ADC1 and ADC2 Trigger 11.9.3 Fast interleaved mode This mode can be started only on a regular channel group (usually one channel). The source of external trigger comes from the regular channel mux of ADC1.
Page 207: Alternate Trigger Mode
RM0034 Analog-to-digital converter (ADC) After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword.
Page 208: Independent Mode
Analog-to-digital converter (ADC) RM0034 If the injected discontinuous mode is enabled for both ADC1 and ADC2: ● When the 1st trigger occurs, the first injected channel in ADC1 is converted. ● When the 2nd trigger arrives, the first injected channel in ADC2 are converted ●...
Page 209: Combined Injected Simultaneous + Interleaved
RM0034 Analog-to-digital converter (ADC) Figure 38. Alternate + Regular simultaneous 1st trig ADC1 reg ADC1 inj ADC2 reg ADC2 inj synchro not lost 2nd trig If a trigger occurs during an injected conversion that has interrupted a regular conversion, it will be ignored.
Page 210: Temperature Sensor
Analog-to-digital converter (ADC) RM0034 11.10 Temperature sensor The temperature sensor can be used to measure the ambient temperature (T ) of the device. The temperature sensor is internally connected to the ADCx_IN16 input channel which is used to convert the sensor output voltage into a digital value. The recommended sampling time for the temperature sensor is 17.1 µs.
Page 211: Adc Interrupts
RM0034 Analog-to-digital converter (ADC) Reading the temperature To use the sensor: Select the ADCx_IN16 input channel. Select a sample time of 17.1 µs Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake up the temperature sensor from power down mode. Start the ADC conversion by setting the ADON bit (or by external trigger).
Page 212: Adc Registers
Analog-to-digital converter (ADC) RM0034 11.12 ADC registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. 11.12.1 ADC status register (ADC_SR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved Reserved STRT JSTRT JEOC Res.
Page 213: Adc Control Register 1 (Adc_Cr1)
RM0034 Analog-to-digital converter (ADC) 11.12.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 AWDE JAWD Reserved Reserved DUALMOD[3:0] Res. Res. JDISC DISC JAUT JEOC DISCNUM[2:0] SCAN AWDIE EOCIE AWDCH[4:0] Bits 31:24 Reserved, must be kept cleared. Bit 23 AWDEN: Analog watchdog enable on regular channels This bit is set/reset by software.
Page 214 Analog-to-digital converter (ADC) RM0034 Bit 12 JDISCEN: Discontinuous mode on injected channels This bit set and cleared by software to enable/disable discontinuous mode on injected group channels 0: Discontinuous mode on injected channels disabled 1: Discontinuous mode on injected channels enabled Bit 11 DISCEN: Discontinuous mode on regular channels This bit set and cleared by software to enable/disable Discontinuous mode on regular channels.
Page 215: Adc Control Register 2 (Adc_Cr2)
RM0034 Analog-to-digital converter (ADC) Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits These bits are set and cleared by software. They select the input channel to be guarded by the Analog watchdog. 00000: ADC analog input Channel0 00001: ADC analog input Channel1 ..
Page 216 Analog-to-digital converter (ADC) RM0034 Bit 20 EXTTRIG: External trigger conversion mode for regular channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of a regular channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Bits 19:17 EXTSEL[2:0]: External event select for regular group These bits select the external event used to trigger the start of conversion of a regular group:...
Page 217 RM0034 Analog-to-digital converter (ADC) Bits 14:12 JEXTSEL[2:0]: External event select for injected group These bits select the external event used to trigger the start of conversion of an injected group: For ADC1 and ADC2 the assigned triggers are: 000: Timer 1 TRGO event 001: Timer 1 CC4 event 010: Timer 2 TRGO event 011: Timer 2 CC1 event...
Page 218: Adc Sample Time Register 1 (Adc_Smpr1)
Analog-to-digital converter (ADC) RM0034 Bit 1 CONT: Continuous conversion This bit is set and cleared by software. If set conversion takes place continuously till this bit is reset. 0: Single conversion mode 1: Continuous conversion mode Bit 0 ADON: A/D converter ON / OFF This bit is set and cleared by software.
Page 219: Adc Sample Time Register 2 (Adc_Smpr2)
RM0034 Analog-to-digital converter (ADC) 11.12.5 ADC sample time register 2 (ADC_SMPR2) Address offset: 0x10 Reset value: 0x0000 0000 Reserved SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1] Res. SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0] Bits 31:30 Reserved, must be kept cleared. Bits 29:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel.
Page 220: Adc Watchdog High Threshold Register (Adc_Htr)
Analog-to-digital converter (ADC) RM0034 11.12.7 ADC watchdog high threshold register (ADC_HTR) Address offset: 0x24 Reset value: 0x0000 0FFF Reserved HT[11:0] Reserved Bits 31:12 Reserved, must be kept cleared. Bits 11:0 HT[11:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. 11.12.8 ADC watchdog low threshold register (ADC_LTR) Address offset: 0x28...
Page 221: Adc Regular Sequence Register 2 (Adc_Sqr2)
RM0034 Analog-to-digital converter (ADC) Bits 31:24 Reserved, must be kept cleared. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. 0000: 1 conversion 0001: 2 conversions ..
Page 222: Adc Regular Sequence Register 3 (Adc_Sqr3)
Analog-to-digital converter (ADC) RM0034 11.12.11 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x34 Reset value: 0x0000 0000 SQ6[4:0] SQ5[4:0] SQ4[4:1] Reserved SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0] Bits 31:30 Reserved, must be kept cleared. Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 6th in the sequence to be converted.
Page 223: Adc Injected Data Register X (Adc_Jdrx) (X= 1
RM0034 Analog-to-digital converter (ADC) Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence These bits are written by software with the channel number (0..17) assigned as the 4th in the sequence to be converted. Note: Unlike a regular conversion sequence, if JL[1:0] length is less than four, the channels are converted in a sequence starting from (4-JL).
Page 224: 11.12.15 Adc Register Map
Analog-to-digital converter (ADC) RM0034 11.12.15 ADC register map The following table summarizes the ADC registers. Table 56. ADC register map and reset values Offset Register ADC_SR 0x00 Reserved Reset value DUALMOD DISC ADC_CR1 AWDCH[4:0] 0x04 Reserved [3:0] NUM [2:0] Reset value EXTSEL JEXTSEL ADC_CR2...
Page 225 RM0034 Analog-to-digital converter (ADC) Table 56. ADC register map and reset values (continued) Offset Register ADC_JDR1 JDATA[15:0] 0x3C Reserved Reset value ADC_JDR2 JDATA[15:0] 0x40 Reserved Reset value ADC_JDR3 JDATA[15:0] 0x44 Reserved Reset value ADC_JDR4 JDATA[15:0] 0x48 Reserved Reset value ADC_DR ADC2DATA[15:0] Regular DATA[15:0] 0x4C...
Page 226: Digital-To-Analog Converter (Dac)
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to connectivity line and high-density STM32F101xx and STM32F103xx devices only. 12.1 DAC introduction The DAC module is a 12-bit, voltage output digital-to-analog converter.
Page 227: Table 57. Dac Pins
RM0034 Digital-to-analog converter (DAC) Figure 42. DAC channel block diagram DAC control register TSELx[2:0] bits SWTR IGx TIM2_T RGO DMAENx TIM4_T RGO TIM5_T RGO TIM6_T RGO TIM7_T RGO TIM8_T RGO EXTI_9 DM A req ue stx Control logicx TENx 12-bit DHRx MAMPx[3:0] bits trianglex...
Page 228: Dac Functional Description
Digital-to-analog converter (DAC) RM0034 12.3 DAC functional description 12.3.1 DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time t WAKEUP Note: The ENx bit enables the analog DAC Channelx macrocell only.
Page 229: Dac Conversion
RM0034 Digital-to-analog converter (DAC) Figure 43. Data registers in single DAC channel mode 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710 Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR8RD [7:0] bits (stored into DHR1[11:4] bits) and data for DAC channel2 to be loaded into DAC_DHR8RD [15:8] bits (stored into DHR2[11:4] bits) –...
Page 230: Dac Output Voltage
Digital-to-analog converter (DAC) RM0034 Figure 45. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK 0x1AC Output voltage 0x1AC available on DAC_OUT pin SETTLING ai14711b 12.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V REF+ The analog output voltages on each DAC channel pin are determined by the following equation:...
Page 231: Dma Request
RM0034 Digital-to-analog converter (DAC) TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx-to- DAC_DORx register transfer. 12.3.7 DMA request Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.
Page 232: Triangle-Wave Generation
Digital-to-analog converter (DAC) RM0034 Figure 47. DAC conversion (SW trigger enabled) with LFSR wave generation APB1_CLK 0x00 0xD55 0xAAA SWTRIG ai14714 Note: DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register. 12.3.9 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
Page 233: Dual Dac Channel Conversion
RM0034 Digital-to-analog converter (DAC) Figure 49. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK 0xABE 0xABE 0xABF 0xAC0 SWTRIG ai14714 Note: DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register. MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.
Page 234: Independent Trigger With Same Lfsr Generation
Digital-to-analog converter (DAC) RM0034 12.4.2 Independent trigger with same LFSR generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits ●...
Page 235: Independent Trigger With Different Triangle Generation
RM0034 Digital-to-analog converter (DAC) DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later).
Page 236: Simultaneous Trigger With Same Lfsr Generation
Digital-to-analog converter (DAC) RM0034 12.4.8 Simultaneous trigger with same LFSR generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits ●...
Page 237: Simultaneous Trigger With Different Triangle Generation
RM0034 Digital-to-analog converter (DAC) added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. 12.4.11 Simultaneous trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: ●...
Page 238 Digital-to-analog converter (DAC) RM0034 Bit 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ Triangle Amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ Triangle Amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ Triangle Amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ Triangle Amplitude equal to 15...
Page 239 RM0034 Digital-to-analog converter (DAC) Bit 12 DMAEN1: DAC channel1 DMA enable This bit is set and cleared by software. 0: DAC channel1 DMA mode disabled 1: DAC channel1 DMA mode enabled Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode.
Page 240: Dac Software Trigger Register (Dac_Swtrigr)
Digital-to-analog converter (DAC) RM0034 Bit 0 EN1: DAC channel1 enable This bit set and cleared by software to enable/disable DAC channel1. 0: DAC channel1 disabled 1: DAC channel1 enabled 12.5.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Reserved SWTRI SWTRI...
Page 241: Dac Channel1 12-Bit Left Aligned Data Holding Register
RM0034 Digital-to-analog converter (DAC) 12.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Reserved DACC1DHR[11:0] Reserved Bits 31:16 Reserved. Bit 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel1. Bits 3:0 Reserved.
Page 242: Dac Channel2 12-Bit Left Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0034 12.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) Address offset: 0x18 Reset value: 0x0000 0000 Reserved DACC2DHR[11:0] Reserved Bits 31:16 Reserved. Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. Bits 3:0 Reserved.
Page 243: Dual Dac 12-Bit Left Aligned Data Holding Register
RM0034 Digital-to-analog converter (DAC) Bits 15:12 Reserved. Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel1. 12.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) Address offset: 0x24 Reset value: 0x0000 0000 DACC2DHR[11:0] Reserved...
Page 244: Dac Channel1 Data Output Register (Dac_Dor1)
Digital-to-analog converter (DAC) RM0034 12.5.12 DAC channel1 data output register (DAC_DOR1) Address offset: 0x2C Reset value: 0x0000 0000 Reserved DACC1DOR[11:0] Reserved Bits 31:12 Reserved. Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output These bits are read only, they contain data output for DAC channel1. 12.5.13 DAC channel2 data output register (DAC_DOR2) Address offset: 0x30...
Page 245: Dac Register Map
RM0034 Digital-to-analog converter (DAC) 12.5.14 DAC register map The following table summarizes the DAC registers. Table 59. DAC register map dress Name offset TSEL2[2: TSEL1[2: 0x00 DAC_CR MAMP2[3:0] E2[2: MAMP1[3:0] E1[2: Reserved Reserved DAC_SWTRI 0x04 Reserved DAC_DHR12 0x08 Reserved DACC1DHR[11:0] DAC_DHR12 0x0C Reserved...
Page 246: Advanced-Control Timers (Tim1&Tim8)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 247 RM0034 Advanced-control timers (TIM1&TIM8) ● Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare –...
Page 248: Figure 50. Advanced-Control Timer Block Diagram
Advanced-control timers (TIM1&TIM8) RM0034 Figure 50. Advanced-control timer block diagram Internal Clock (CK_INT) CK_TIM18 from RCC ETRF Trigger ETRP Controller Polarity Selection & Edge TRGO Input Filter TIMx_ETR Detector & Prescaler to other timers ITR0 to DAC/ADC ITR1 Slave Reset, Enable, Up/Down, Count ITR2 Mode TRGI...
Page 249: Tim1&Tim8 Functional Description
RM0034 Advanced-control timers (TIM1&TIM8) 13.3 TIM1&TIM8 functional description 13.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 250: Counter Modes
Advanced-control timers (TIM1&TIM8) RM0034 Figure 51. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 52.
Page 251: Figure 53. Counter Timing Diagram, Internal Clock Divided By 1
RM0034 Advanced-control timers (TIM1&TIM8) preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent).
Page 252: Figure 55. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1&TIM8) RM0034 Figure 55. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 56. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register...
Page 253: Figure 58. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
RM0034 Advanced-control timers (TIM1&TIM8) Figure 58. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register Write a new value in TIMx_ARR...
Page 254: Figure 59. Counter Timing Diagram, Internal Clock Divided By 1
Advanced-control timers (TIM1&TIM8) RM0034 The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 59. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV)
Page 255: Figure 62. Counter Timing Diagram, Internal Clock Divided By N
RM0034 Advanced-control timers (TIM1&TIM8) Figure 62. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 63. Counter timing diagram, update event when repetition counter is not used CK_PSC Timer clock = CK_CNT...
Page 256: Figure 64. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timers (TIM1&TIM8) RM0034 In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
Page 257: Figure 66. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
RM0034 Advanced-control timers (TIM1&TIM8) Figure 66. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0035 Counter overflow Update event (UEV) Update interrupt flag (UIF) Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow Figure 67.
Page 258: Repetition Counter
Advanced-control timers (TIM1&TIM8) RM0034 Figure 69. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC Timer clock = CK_CNT Counter register F8 F9 FA FB FC 35 34 33 32 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active register...
Page 259: Figure 70. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
RM0034 Advanced-control timers (TIM1&TIM8) Figure 70. Update rate examples depending on mode and TIMx_RCR register settings Center-aligned mode Edge-aligned mode Upcounting Downcounting Counter TIMx_CNT TIMx_RCR = 0 TIMx_RCR = 1 TIMx_RCR = 2 TIMx_RCR = 3 TIMx_RCR re-synchronization (by SW) (by SW) (by SW) UEV Update Event: Preload registers transferred to active registers and update interrupt generated...
Page 260: Clock Selection
Advanced-control timers (TIM1&TIM8) RM0034 13.3.4 Clock selection The counter clock can be provided by the following clock sources: ● Internal clock (CK_INT) ● External clock mode1: external input pin ● External clock mode2: external trigger input ETR ● Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2.
Page 261: Figure 73. Control Circuit In External Clock Mode 1
RM0034 Advanced-control timers (TIM1&TIM8) For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 262: Capture/Compare Channels
Advanced-control timers (TIM1&TIM8) RM0034 For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 263: Figure 76. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0034 Advanced-control timers (TIM1&TIM8) Figure 76. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1F_Rising TI1F TI1FP1 filter Edge downcounter Detector TI1F_Falling TI2FP1 IC1PS divider /1, /2, /4, /8 ICF[3:0] CC1P (from slave mode TIMx_CCMR1 TIMx_CCER controller) TI2F_rising...
Page 264: Input Capture Mode
Advanced-control timers (TIM1&TIM8) RM0034 Figure 78. Output stage of capture/compare channel (channel 1 to 3) Output enable ‘0’ circuit OC1_DT CC1P CNT>CCR1 OC1REF Output mode Dead-time TIM1_CCER CNT=CCR1 controller generator OC1N_DT OC1N Output ‘0’ enable circuit CC1NE CC1E TIM1_CCER OC1CE OC1M[2:0] DTG[7:0] CC1NE...
Page 265: Pwm Input Mode
RM0034 Advanced-control timers (TIM1&TIM8) The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: ● Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register.
Page 266: Forced Output Mode
Advanced-control timers (TIM1&TIM8) RM0034 For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): ● Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).
Page 267: Output Compare Mode
RM0034 Advanced-control timers (TIM1&TIM8) Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. 13.3.9 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
Page 268: Pwm Mode
Advanced-control timers (TIM1&TIM8) RM0034 Figure 81. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIM1_CNT 0039 003A B200 B201 003B TIM1_CCR1 003A B201 oc1ref=OC1 Match detected on CCR1 Interrupt generated if enabled 13.3.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 269: Figure 82. Edge-Aligned Pwm Waveforms (Arr=8)
RM0034 Advanced-control timers (TIM1&TIM8) PWM edge-aligned mode ● Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 250. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 270: Figure 83. Center-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1&TIM8) RM0034 Figure 83. Center-aligned PWM waveforms (ARR=8) Counter register OCxREF CCRx = 4 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx = 7 CMS=10 or 11 CCxIF OCxREF CCRx = 8 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx > 8 CMS=01 CCxIF CMS=10...
Page 271: Complementary Outputs And Dead-Time Insertion
RM0034 Advanced-control timers (TIM1&TIM8) 13.3.11 Complementary outputs and dead-time insertion The advanced-control timers (TIM1&TIM8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of level- shifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN)
Page 272: Using The Break Function
Advanced-control timers (TIM1&TIM8) RM0034 Figure 86. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 13.4.18: Break and dead-time register (TIMx_BDTR) on page 307 for delay calculation.
Page 273 RM0034 Advanced-control timers (TIM1&TIM8) When a break occurs (selected level on the break input): ● The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the OSSI bit). This feature functions even if the MCU oscillator is off.
Page 274: Figure 87. Output Behavior In Response To A Break
Advanced-control timers (TIM1&TIM8) RM0034 Figure 87. Output behavior in response to a break. BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay...
Page 275: Clearing The Ocxref Signal On An External Event
RM0034 Advanced-control timers (TIM1&TIM8) 13.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs.
Page 276: 6-Step Pwm Generation
Advanced-control timers (TIM1&TIM8) RM0034 13.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 277: One-Pulse Mode
RM0034 Advanced-control timers (TIM1&TIM8) 13.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 278: Encoder Interface Mode
Advanced-control timers (TIM1&TIM8) RM0034 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● The t is defined by the value written in the TIMx_CCR1 register. DELAY ● The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 279: Table 60. Counting Direction Versus Encoder Signals
RM0034 Advanced-control timers (TIM1&TIM8) repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position.
Page 280: Figure 91. Example Of Counter Operation In Encoder Interface Mode
Advanced-control timers (TIM1&TIM8) RM0034 Figure 91. Example of counter operation in encoder interface mode. forward jitter backward jitter forward Counter down Figure 92 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 92.
Page 281: Timer Input Xor Function
RM0034 Advanced-control timers (TIM1&TIM8) 13.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 282: Figure 93. Example Of Hall Sensor Interface
Advanced-control timers (TIM1&TIM8) RM0034 written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF). Figure 93 describes this example. Figure 93. Example of hall sensor interface TIH1 TIH2 TIH3...
Page 283: Timx And External Trigger Synchronization
RM0034 Advanced-control timers (TIM1&TIM8) 13.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 284: Figure 95. Control Circuit In Gated Mode
Advanced-control timers (TIM1&TIM8) RM0034 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: ● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 285: Figure 96. Control Circuit In Trigger Mode
RM0034 Advanced-control timers (TIM1&TIM8) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: ● Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000).
Page 286: Timer Synchronization
Advanced-control timers (TIM1&TIM8) RM0034 Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01in TIMx_CCMR1 register to select only the input capture source –...
Page 287: Tim1&Tim8 Registers
RM0034 Advanced-control timers (TIM1&TIM8) 13.4 TIM1&TIM8 registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. 13.4.1 Control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 CKD[1:0] ARPE CMS[1:0] UDIS Reserved Bits 15:10 Reserved, always read as 0 Bits 9:8 CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t...
Page 288: Control Register 2 (Timx_Cr2)
Advanced-control timers (TIM1&TIM8) RM0034 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 289 RM0034 Advanced-control timers (TIM1&TIM8) Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register).
Page 290: Slave Mode Control Register (Timx_Smcr)
Advanced-control timers (TIM1&TIM8) RM0034 13.4.3 Slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Res. Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge.
Page 291 RM0034 Advanced-control timers (TIM1&TIM8) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 292: Dma/Interrupt Enable Register (Timx_Dier)
Advanced-control timers (TIM1&TIM8) RM0034 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 293 RM0034 Advanced-control timers (TIM1&TIM8) Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled. Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled. Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled.
Page 294: Status Register (Timx_Sr)
Advanced-control timers (TIM1&TIM8) RM0034 13.4.5 Status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC4O CC3O CC2O CC1O Res. COMIF CC4IF CC3IF CC2IF CC1IF Reserved rc_w0 rc_w0 rc_w0 rc_w0 Res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bit 15:13 Reserved, always read as 0. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag...
Page 295: Event Generation Register (Timx_Egr)
RM0034 Advanced-control timers (TIM1&TIM8) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 296: Capture/Compare Mode Register 1 (Timx_Ccmr1)
Advanced-control timers (TIM1&TIM8) RM0034 Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output.
Page 297 RM0034 Advanced-control timers (TIM1&TIM8) Output compare mode: Bit 15 OC2CE: Output Compare 2 clear enable Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input.
Page 298 Advanced-control timers (TIM1&TIM8) RM0034 Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 299 RM0034 Advanced-control timers (TIM1&TIM8) Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 300: Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timers (TIM1&TIM8) RM0034 13.4.8 Capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4M[2:0] OC3M[2:0] CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable...
Page 301: Capture/Compare Enable Register (Timx_Ccer)
RM0034 Advanced-control timers (TIM1&TIM8) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output.
Page 302 Advanced-control timers (TIM1&TIM8) RM0034 Bit 7 CC2NP: Capture/Compare 2 complementary output polarity refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity 0: OC1N active high.
Page 303: Table 62. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
RM0034 Advanced-control timers (TIM1&TIM8) Table 62. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not Output Disabled (not driven by driven by the timer) the timer) OCx=0, OCx_EN=0...
Page 304: Counter (Timx_Cnt)
Advanced-control timers (TIM1&TIM8) RM0034 13.4.10 Counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 13.4.11 Prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1).
Page 305: Repetition Counter Register (Timx_Rcr)
RM0034 Advanced-control timers (TIM1&TIM8) 13.4.13 Repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 Reserved REP[7:0] Res. Bits 15:8 Reserved, always read as 0. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 306: Capture/Compare Register 2 (Timx_Ccr2)
Advanced-control timers (TIM1&TIM8) RM0034 13.4.15 Capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 307: Capture/Compare Register 4 (Timx_Ccr4)
RM0034 Advanced-control timers (TIM1&TIM8) 13.4.17 Capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 308 Advanced-control timers (TIM1&TIM8) RM0034 Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 309: Dma Control Register (Timx_Dcr)
RM0034 Advanced-control timers (TIM1&TIM8) Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 310: Dma Address For Full Transfer (Timx_Dmar)
Advanced-control timers (TIM1&TIM8) RM0034 Bits 4:0 DBA[4:0]: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2,...
Page 311 RM0034 Advanced-control timers (TIM1&TIM8) Table 63. TIM1&TIM8 register map and reset values (continued) Offset Register TIMx_CCMR1 OC2M CC2S OC1M CC1S Output Compare [2:0] [1:0] [2:0] [1:0] Reserved mode Reset value 0x18 TIMx_CCMR1 CC2S CC1S IC2F[3:0] IC1F[3:0] Input Capture [1:0] [1:0] Reserved [1:0] [1:0]...
Page 312: General-Purpose Timer (Timx)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 313: Timx Main Features
RM0034 General-purpose timer (TIMx) 14.2 TIMx main features General purpose TIMx (TIM2, TIM3, TIM4 and TIM5) timer features include: ● 16-bit up, down, up/down auto-reload counter. ● 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65535. ●...
Page 314: Timx Functional Description
General-purpose timer (TIMx) RM0034 Figure 98. General-purpose timer block diagram Internal Clock (CK_INT) TIMxCLK from RCC ETRF ETRP Polarity Selection & Edge Input Filter TIMx_ETR Detector & Prescaler TRGO ITR0 Trigger to other timers Controller ITR1 to DAC/ADC ITR2 TRGI Slave ITR3 Reset, Enable, Up/Down, Count,...
Page 315: Figure 99. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0034 General-purpose timer (TIMx) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
Page 316: Counter Modes
General-purpose timer (TIMx) RM0034 Figure 100. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter 14.3.2...
Page 317: Figure 101. Counter Timing Diagram, Internal Clock Divided By 1
RM0034 General-purpose timer (TIMx) Figure 101. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 102.
Page 318: Figure 104. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timer (TIMx) RM0034 Figure 104. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 105. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN...
Page 319: Figure 106. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
RM0034 General-purpose timer (TIMx) Figure 106. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 320: Figure 107. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timer (TIMx) RM0034 Figure 107. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) Figure 108.
Page 321: Figure 110. Counter Timing Diagram, Internal Clock Divided By N
RM0034 General-purpose timer (TIMx) Figure 110. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 111. Counter timing diagram, Update event when repetition counter is not used CK_INT CNT_EN...
Page 322: Figure 112. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
General-purpose timer (TIMx) RM0034 In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event.
Page 323: Figure 114. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
RM0034 General-purpose timer (TIMx) Figure 114. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_INT CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0035 Counter overflow (cnt_ovf) Update event (UEV) Update interrupt flag (UIF) Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow Figure 115.
Page 324: Clock Selection
General-purpose timer (TIMx) RM0034 Figure 117. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register F8 F9 FA FB FC 35 34 33 32 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR...
Page 325: Figure 118. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0034 General-purpose timer (TIMx) Figure 118. Control circuit in normal mode, internal clock divided by 1 CK_INT CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC COUNTER REGISTER 32 33 34 35 36 01 02 03 04 05 06 07 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register.
Page 326: Figure 120. Control Circuit In External Clock Mode 1
General-purpose timer (TIMx) RM0034 The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 120. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 External clock source mode 2...
Page 327: Capture/Compare Channels
RM0034 General-purpose timer (TIMx) Figure 122. Control circuit in external clock mode 2 MASTER CNT_EN ETRP ETRF Counter clock = CK_CNT = CK_PSC Counter register 14.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 328: Figure 124. Capture/Compare Channel 1 Main Circuit
General-purpose timer (TIMx) RM0034 Figure 124. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H write_in_progress read CCR1H read_in_progress write CCR1L Capture/Compare Preload Register read CCR1L CC1S[1] output compare_transfer capture_transfer mode CC1S[0] input CC1S[1] OC1PE mode OC1PE Capture/Compare Shadow Register CC1S[0] TIMx_CCMR1 (from time...
Page 329: Input Capture Mode
RM0034 General-purpose timer (TIMx) 14.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 330: Pwm Input Mode
General-purpose timer (TIMx) RM0034 14.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: ● Two ICx signals are mapped on the same TIx input. ● These 2 ICx signals are active on edges with opposite polarity. ●...
Page 331: Output Compare Mode
RM0034 General-purpose timer (TIMx) To force an output compare signal (ocxref/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. e.g.: CCxP=0 (OCx active high) =>...
Page 332: Pwm Mode
General-purpose timer (TIMx) RM0034 Figure 127. Output compare mode, toggle on OC1. Write B201h in the CC1R register B200 B201 TIMx_CNT 0039 003A 003B TIMx_CCR1 003A B201 OC1REF=OC1 Match detected on CCR1 Interrupt generated if enabled 14.3.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 333: Figure 128. Edge-Aligned Pwm Waveforms (Arr=8)
RM0034 General-purpose timer (TIMx) PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Section : upcounting mode on page 316. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low.
Page 334: Figure 129. Center-Aligned Pwm Waveforms (Arr=8)
General-purpose timer (TIMx) RM0034 Figure 129. Center-aligned PWM waveforms (ARR=8) Counter register OCxREF CCRx = 4 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx = 7 CMS=10 or 11 CCxIF OCxREF CCRx = 8 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx > 8 CMS=01 CCxIF CMS=10...
Page 335: One Pulse Mode
RM0034 General-purpose timer (TIMx) 14.3.10 One pulse mode One Pulse Mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Page 336: Clearing The Ocxref Signal On An External Event
General-purpose timer (TIMx) RM0034 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● The t is defined by the value written in the TIMx_CCR1 register. DELAY ● The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 337: Encoder Interface Mode
RM0034 General-purpose timer (TIMx) Figure 131. Clearing TIMx OCxREF (CCRx) counter (CNT) ETRF OCxREF (OCxCE=’0’) OCxREF (OCxCE=’1’) OCREF_CLR OCREF_CLR becomes high still high 14.3.12 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’...
Page 338: Table 64. Counting Direction Versus Encoder Signals
General-purpose timer (TIMx) RM0034 Table 64. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal Active edge signal (TI1FP1 for Rising Falling Rising Falling TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 339: Timer Input Xor Function
RM0034 General-purpose timer (TIMx) Figure 133. Example of encoder interface mode with IC1FP1 polarity inverted. forward jitter backward jitter forward Counter down down The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode.
Page 340: Figure 134. Control Circuit In Reset Mode
General-purpose timer (TIMx) RM0034 ● Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. ● Start the counter by writing CEN=1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge.
Page 341: Figure 135. Control Circuit In Gated Mode
RM0034 General-purpose timer (TIMx) Figure 135. Control circuit in gated mode CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 32 33 35 36 37 38 Write TIF=0 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: ●...
Page 342: Timer Synchronization
General-purpose timer (TIMx) RM0034 In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: –...
Page 343: Figure 138. Master/Slave Timer Example
RM0034 General-purpose timer (TIMx) Using one timer as prescaler for the another Figure 138. Master/Slave timer example TIMER 1 TIMER 2 Clock Master Slave CK_PSC TRGO1 ITR1 mode mode control Counter Prescaler Counter Prescaler control Input trigger selection For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 138.
Page 344: Figure 139. Gating Timer 2 With Oc1Ref Of Timer 1
General-purpose timer (TIMx) RM0034 Figure 139. Gating timer 2 with OC1REF of timer 1 CK_INT TIMER1-OC1REF TIMER1-CNT TIMER2-CNT 3045 3046 3047 3048 TIMER 2-TIF Write TIF=0 In the example in Figure 139, the Timer 2 counter and prescaler are not initialized before being started.
Page 345: Figure 140. Gating Timer 2 With Enable Of Timer 1
RM0034 General-purpose timer (TIMx) Figure 140. Gating timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT TIMER2-CNT TIMER2-CNT_INIT TIMER2 write CNT TIMER 2-TIF Write TIF=0 Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to Figure 138 for connections.
Page 346: Figure 142. Triggering Timer 2 With Enable Of Timer 1
General-purpose timer (TIMx) RM0034 As in the previous example, you can initialize both counters before starting counting. Figure 142 shows the behavior with the same configuration as in Figure 141 but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register). Figure 142.
Page 347: Debug Mode
RM0034 General-purpose timer (TIMx) counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2): ● Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the TIM1_CR2 register).
Page 348: Timx Registers
General-purpose timer (TIMx) RM0034 14.4 TIMx registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. 14.4.1 Control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 CKD[1:0] ARPE UDIS Reserved Bits 15:10 Reserved, always read as 0 Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),...
Page 349: Control Register 2 (Timx_Cr2)
RM0034 General-purpose timer (TIMx) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 350: Slave Mode Control Register (Timx_Smcr)
General-purpose timer (TIMx) RM0034 Bits 6:4 MMS: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
Page 351 RM0034 General-purpose timer (TIMx) Bit 14 ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled. 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Page 352: Table 65. Timx Internal Trigger Connection
General-purpose timer (TIMx) RM0034 Bits 6:4 TS: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0). TIM1 001: Internal Trigger 1 (ITR1). TIM2 010: Internal Trigger 2 (ITR2). TIM3 011: Internal Trigger 3 (ITR3).
Page 353: Dma/Interrupt Enable Register (Timx_Dier)
RM0034 General-purpose timer (TIMx) 14.4.4 DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 CC4IE CC3IE CC2IE CC1IE Res. Res. Bit 15 Reserved, always read as 0. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled.
Page 354: Status Register (Timx_Sr)
General-purpose timer (TIMx) RM0034 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled.
Page 355: Event Generation Register (Timx_Egr)
RM0034 General-purpose timer (TIMx) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 356: Capture/Compare Mode Register 1 (Timx_Ccmr1)
General-purpose timer (TIMx) RM0034 Bit 2 CC2G: Capture/compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 357 RM0034 General-purpose timer (TIMx) Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1.
Page 358 General-purpose timer (TIMx) RM0034 Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON.
Page 359 RM0034 General-purpose timer (TIMx) Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 360: Capture/Compare Mode Register 2 (Timx_Ccmr2)
General-purpose timer (TIMx) RM0034 14.4.8 Capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4M[2:0] OC3M[2:0] CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable...
Page 361: Capture/Compare Enable Register (Timx_Ccer)
RM0034 General-purpose timer (TIMx) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output.
Page 362: Counter (Timx_Cnt)
General-purpose timer (TIMx) RM0034 Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bits 3:2 Reserved, always read as 0. Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high. 1: OC1 active low. CC1 channel configured as input: This bit selects whether IC1 or IC1 is used for trigger or capture operations.
Page 363: Prescaler (Timx_Psc)
RM0034 General-purpose timer (TIMx) 14.4.11 Prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event. 14.4.12 Auto-reload register (TIMx_ARR) Address offset: 0x2C...
Page 364: Capture/Compare Register 2 (Timx_Ccr2)
General-purpose timer (TIMx) RM0034 14.4.14 Capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 365: Capture/Compare Register 4 (Timx_Ccr4)
RM0034 General-purpose timer (TIMx) 14.4.16 Capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value 1/ if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 366: Dma Address For Full Transfer (Timx_Dmar)
General-purpose timer (TIMx) RM0034 14.4.18 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write access to the DMAR register accesses the register located at the address: “(TIMx_CR1 address) + DBA + (DMA index)”...
Page 367 RM0034 General-purpose timer (TIMx) Table 67. TIMx register map and reset values (continued) Offset Register TIMx_CCMR2 OC4M CC4S OC3M CC3S Output Compare [2:0] [1:0] [2:0] [1:0] Reserved mode Reset value 0x1C TIMx_CCMR2 CC4S CC3S IC4F[3:0] IC3F[3:0] Input Capture [1:0] [1:0] Reserved [1:0] [1:0]...
Page 368: Basic Timers (Tim6&Tim7)
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to high-density STM32F101xx and STM32F103xx devices, and to connectivity line devices only. 15.1 TIM6&TIM7 introduction...
Page 369: Tim6&Tim7 Functional Description
RM0034 Basic timers (TIM6&TIM7) Figure 144. Basic timer block diagram TRGO Trigger Internal clock (CK_INT) to DAC TIMxCLK from RCC controller Reset, Enable, Count, Controller Auto-reload Register Stop, Clear or up CK_PSC CK_CNT ± Prescaler COUNTER Flag Preload registers transferred to active registers on U event according to control bit event interrupt &...
Page 370: Figure 145. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timers (TIM6&TIM7) RM0034 Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.
Page 371: Counting Mode
RM0034 Basic timers (TIM6&TIM7) 15.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 372: Figure 148. Counter Timing Diagram, Internal Clock Divided By 2
Basic timers (TIM6&TIM7) RM0034 Figure 148. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 149. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN TImer clock = CK_CNT...
Page 373: Clock Source
RM0034 Basic timers (TIM6&TIM7) Figure 151. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) CK_INT CNT_EN Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register...
Page 374: Debug Mode
Basic timers (TIM6&TIM7) RM0034 Figure 153. Control circuit in normal mode, internal clock divided by 1 CK_INT CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 32 33 34 35 36 01 02 03 04 05 06 07 15.3.4 Debug mode When the microcontroller enters the debug mode (Cortex-M3 core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP...
Page 375 RM0034 Basic timers (TIM6&TIM7) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: –...
Page 376: Control Register 2 (Timx_Cr2)
Basic timers (TIM6&TIM7) RM0034 15.4.2 Control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 MMS[2:0] Reserved Reserved Bits 15:7 Reserved, always read as 0. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 377: Status Register (Timx_Sr)
RM0034 Basic timers (TIM6&TIM7) 15.4.4 Status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Reserved rc_w0 Bits 15:1 Reserved, always read as 0. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred.
Page 378: Prescaler (Timx_Psc)
Basic timers (TIM6&TIM7) RM0034 15.4.7 Prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded into the active prescaler register at each update event. 15.4.8 Auto-reload register (TIMx_ARR) Address offset: 0x2C...
Page 379: Tim6&Tim7 Register Map
RM0034 Basic timers (TIM6&TIM7) 15.4.9 TIM6&TIM7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 68. TIM6&TIM7 register map and reset values Offset Register TIMx_CR1 0x00 Reserved Reset value TIMx_CR2 MMS[2:0] 0x04 Reserved Reset value 0x08...
Page 380: Real-Time Clock (Rtc)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 381: Rtc Main Features
RM0034 Real-time clock (RTC) 16.2 RTC main features ● Programmable prescaler: division factor up to 2 ● 32-bit programmable counter for long-term measurement ● Two separate clocks: PCLK1 for the APB1 interface and RTC clock (must be at least four times slower than the PCLK1 clock) ●...
Page 382: Figure 154. Rtc Simplified Block Diagram
Real-time clock (RTC) RM0034 Figure 154. RTC simplified block diagram APB1 bus PCLK1 APB1 interface not powered in Standby RTCCLK Backup domain RTC_CR RTC_PRL RTC_Second SECF 32-bit programmable Reload SECIE counter RTC_Overflow TR_CLK RTC_CNT RTC_DIV rising OWIE edge RTC_Alarm ALRF RTC prescaler ALRIE RTC_ALR...
Page 383: Resetting Rtc Registers
RM0034 Real-time clock (RTC) 16.3.2 Resetting RTC registers All system registers are asynchronously reset by a System Reset or Power Reset, except for RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV. The RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup Domain reset.
Page 384: Rtc Flag Assertion
Real-time clock (RTC) RM0034 16.3.5 RTC flag assertion The RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update of the RTC Counter. The RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the counter reaches 0x0000.
Page 385: Rtc Registers
RM0034 Real-time clock (RTC) 16.4 RTC registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. 16.4.1 RTC control register high (RTC_CRH) Address offset: 0x00 Reset value: 0x0000 OWIE ALRIE SECIE Reserved Bits 15:3 Reserved, forced by hardware to 0. Bit 2 OWIE: Overflow interrupt enable 0: Overflow interrupt is masked.
Page 386: Rtc Control Register Low (Rtc_Crl)
Real-time clock (RTC) RM0034 16.4.2 RTC control register low (RTC_CRL) Address offset: 0x04 Reset value: 0x0020 RTOFF ALRF SECF Reserved rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:6 Reserved, forced by hardware to 0. Bit 5 RTOFF: RTC operation OFF With this bit the RTC reports the status of the last write operation performed on its registers, indicating if it has been completed or not.
Page 387: Rtc Prescaler Load Register (Rtc_Prlh / Rtc_Prll)
RM0034 Real-time clock (RTC) The functions of the RTC are controlled by this control register. It is not possible to write to the RTC_CR register while the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 16.3.4 on page 383).
Page 388: Rtc Prescaler Divider Register (Rtc_Divh / Rtc_Divl)
Real-time clock (RTC) RM0034 RTC prescaler load register low (RTC_PRLL) Address offset: 0x0C Write only (see Section 16.3.4 on page 383) Reset value: 0x8000 PRL[15:0] Bits 15:0 PRL[15:0]: RTC prescaler reload value low These bits are used to define the counter clock frequency according to the following formula: /(PRL[19:0]+1) TR_CLK RTCCLK...
Page 389: Rtc Counter Register (Rtc_Cnth / Rtc_Cntl)
RM0034 Real-time clock (RTC) 16.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) The RTC core has one 32-bit programmable counter, accessed through two 16-bit registers; the count rate is based on the TR_CLK time reference, generated by the prescaler. RTC_CNT registers keep the counting value of this counter. They are write-protected by bit RTOFF in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’.
Page 390: Rtc Alarm Register High (Rtc_Alrh / Rtc_Alrl)
Real-time clock (RTC) RM0034 16.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) When the programmable counter reaches the 32-bit value stored in the RTC_ALR register, an alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’.
Page 391: Rtc Register Map
RM0034 Real-time clock (RTC) 16.4.7 RTC register map RTC registers are mapped as 16-bit addressable registers as described in the table below: Table 69. register map and reset values Offset Register RTC_CRH 0x000 Reserved Reset value RTC_CRL 0x004 Reserved Reset value RTC_PRLH PRL[19:16] 0x008...
Page 392: Independent Watchdog (Iwdg)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 393: Hardware Watchdog
RM0034 Independent watchdog (IWDG) 17.3.1 Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and will generate a reset unless the Key register is written by the software before the counter reaches end of count. 17.3.2 Register access protection Write access to the IWDG_PR and IWDG_RLR registers is protected.
Page 394: Iwdg Registers
Independent watchdog (IWDG) RM0034 The LSI can be calibrated so as to compute the IWDG timeout with an acceptable accuracy. For more details refer to LSI calibration on page 17.4 IWDG registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. 17.4.1 Key register (IWDG_KR) Address offset: 0x00...
Page 395: Reload Register (Iwdg_Rlr)
RM0034 Independent watchdog (IWDG) Bits 31:3 Reserved, read as 0. Bits 2:0 PR[2:0]: Prescaler divider These bits are write access protected seeSection 17.3.2. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider.
Page 396: Status Register (Iwdg_Sr)
Independent watchdog (IWDG) RM0034 17.4.4 Status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) Reserved Reserved Bits 31:2 Reserved Bit 1 RVU: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the V voltage domain (takes up to 5 RC 40 kHz cycles).
Page 397: Window Watchdog (Wwdg)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 398: Figure 158. Watchdog Block Diagram
Window watchdog (WWDG) RM0034 Figure 158. Watchdog block diagram Watchdog configuration register (WWDG_CFR) RESET comparator = 1 when T6:0 > W6:0 Write WWDG_CR Watchdog control register (WWDG_CR) WDGA 6-bit downcounter (CNT) PCLK1 (from RCC clock controller) WDG prescaler (WDGTB) The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset.
Page 399: How To Program The Watchdog Timeout
RM0034 Window watchdog (WWDG) 18.4 How to program the watchdog timeout Figure 159 shows the linear relationship between the 6-bit value to be loaded in the watchdog counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If more precision is needed, use the formulae in Figure 159.
Page 400: Debug Mode
Window watchdog (WWDG) RM0034 18.5 Debug mode When the microcontroller enters debug mode (Cortex-M3 core halted), the WWDG counter either continues to work normally or stops, depending on DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to Section 30.15.2: Debug support for timers, watchdog, bxCAN and I 18.6 Debug registers...
Page 401: Status Register (Wwdg_Sr)
RM0034 Window watchdog (WWDG) Bit 31:10 Reserved Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 40h. This interrupt is only cleared by hardware after a reset. Bits 8:7 WDGTB[1:0]: Timer base The time base of the prescaler can be modified as follows: 00: CK Counter Clock (PCLK1 div 4096) div 1 01: CK Counter Clock (PCLK1 div 4096) div 2...
Page 402: Flexible Static Memory Controller (Fsmc)
Medium-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 403: Block Diagram
RM0034 Flexible static memory controller (FSMC) ● Write FIFO, 16 words long, each word 32 bits wide. This makes it possible to write to slow memories and free the AHB quickly for other transactions. If a new transaction is started to the FSMC, first the FIFO is drained The FSMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up.
Page 404: Ahb Interface
Flexible static memory controller (FSMC) RM0034 19.3 AHB interface The AHB slave interface enables internal CPUs and other bus master peripherals to access the external static memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16 or 8 bits wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses.
Page 405: External Device Address Mapping
RM0034 Flexible static memory controller (FSMC) 19.4 External device address mapping From the FSMC point of view, the external memory is divided into 4 fixed-size banks of 256 Mbytes each (Refer to Figure 161): ● Bank 1 used to address up to 4 NOR Flash or PSRAM memory devices. This bank is split into 4 NOR/PSRAM regions with 4 dedicated Chip Select.
Page 406: Nand/Pc Card Address Mapping
Flexible static memory controller (FSMC) RM0034 HADDR[25:0] contain the external memory address. Since HADDR is a byte address whereas the memory is addressed in words, the address actually issued to the memory varies according to the memory data width, as shown in the following table. Table 74.
Page 407: Nor Flash/Psram Controller
RM0034 Flexible static memory controller (FSMC) For NAND Flash memory, the common and attribute memory spaces are subdivided into three sections (see in Table 76 below) located in the lower 256 Kbytes: ● Data section (first 64 Kbytes in the common/attribute memory space) ●...
Page 408: External Memory Interface Signals
Flexible static memory controller (FSMC) RM0034 The programmable memory parameters include access timings (see Table 77) and support for wrap and wait management (for PSRAM and NOR Flash accessed in burst mode). Table 77. Programmable NOR/PSRAM access parameters Parameter Function Access mode Unit Min.
Page 409: Table 79. Muxed I/O Nor Flash
RM0034 Flexible static memory controller (FSMC) NOR Flash, multiplexed I/Os Table 79. Muxed I/O NOR Flash FSMC signal name Function Clock (for synchronous burst) A[25:16] Address bus AD[15:0] 16-bit multiplexed, bidirectional address/data bus NE[x] Chip select, x = 1..4 Output enable Write enable Latch enable (this signal is called address valid, NADV, by some NOR NL(=NADV)
Page 410: Supported Memories And Transactions
Flexible static memory controller (FSMC) RM0034 19.5.2 Supported memories and transactions Table 81 below displays the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the FSMC appear in gray. Table 81. NOR Flash/PSRAM supported memories and transactions Allowed/ Memory Device...
Page 411: General Timing Rules
RM0034 Flexible static memory controller (FSMC) 19.5.3 General timing rules Signals synchronization ● All controller output signals change on the rising edge of the internal clock (HCLK) ● In synchronous write mode (PSRAM devices), the output data changes on the falling edge of the memory clock (CLK) 19.5.4 NOR Flash/PSRAM controller timing diagrams...
Page 412: Table 82. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0034 Figure 163. Mode1 write accesses Memory transaction A[25:0] NBL[1:0] 1HCLK D[15:0] data driven by FSMC (ADDSET +1) (DATAST + 1) HCLK cycles HCLK cycles ai14721c The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge.
Page 413: Table 83. Fsmc_Tcrx Bit Fields
RM0034 Flexible static memory controller (FSMC) Table 83. FSMC_TCRx bit fields Bit name Value to set number 31-16 0x0000 Duration of the second access phase (DATAST+1 HCLK cycles) for 15-8 DATAST write accesses, DATAST+3 HCLK cycles for read accesses). This value cannot be 0 (minimum is 1) ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles)
Page 414: Table 84. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0034 Figure 165. ModeA write accesses Memory transaction A[25:0] NBL[1:0] 1HCLK D[15:0] data driven by FSMC (ADDSET +1) (DATAST + 1) HCLK cycles HCLK cycles ai14721c The differences compared with mode1 are the toggling of NOE and the independent read and write timings.
Page 415: Table 85. Fsmc_Tcrx Bit Fields
RM0034 Flexible static memory controller (FSMC) Table 85. FSMC_TCRx bit fields Bit name Value to set number 31-30 29-28 ACCMOD 27-16 0x000 Duration of the second access phase (DATAST+3 HCLK cycles) in 15-8 DATAST read. This value cannot be 0 (minimum is 1) ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in read Table 86.
Page 416: Figure 166. Mode2/B Read Accesses
Flexible static memory controller (FSMC) RM0034 Mode 2/B - NOR Flash Figure 166. Mode2/B read accesses Memory transaction A[25:0] NADV High data driven D[15:0] by memory (ADDSET +1) (DATAST + 1) 2 HCLK HCLK cycles HCLK cycles cycles Data sampled Data strobe ai14724c Figure 167.
Page 417: Table 87. Fsmc_Bcrx Bit Fields
RM0034 Flexible static memory controller (FSMC) Figure 168. ModeB write accesses Memory transaction A[25:0] NADV 1HCLK D[15:0] data driven by FSMC (ADDSET +1) (DATAST + 1) HCLK cycles HCLK cycles ai15110b The differences with mode1 are the toggling of NADV and the independent read and write timings when extended mode is set (Mode B).
Page 418: Table 88. Fsmc_Tcrx Bit Fields
Flexible static memory controller (FSMC) RM0034 Table 88. FSMC_TCRx bit fields Bit number Bit name Value to set 31-30 29-28 ACCMOD 0x1 if extended mode is set 27-16 0x000 Duration of the access second phase (DATAST+3 HCLK cycles) in 15-8 DATAST read.
Page 419: Figure 169. Modec Read Accesses
RM0034 Flexible static memory controller (FSMC) Mode C - NOR Flash - OE toggling Figure 169. ModeC read accesses Memory transaction A[25:0] NADV High data driven D[15:0] by memory (ADDSET +1) (DATAST + 1) 2 HCLK cycles HCLK cycles HCLK cycles Data sampled Data strobe ai14725c...
Page 420: Table 90. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0034 Table 90. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-15 0x0000 EXTMOD 13-10 WAITPOL Meaningful only if bit 15 is 1 BURSTEN FACCEN MWID As needed MTYP 0x02 (NOR Flash) MUXEN MBKEN Table 91.
Page 421: Figure 171. Moded Read Accesses
RM0034 Flexible static memory controller (FSMC) Mode D - asynchronous access with extended address Figure 171. ModeD read accesses Memory transaction A[25:0] NADV High data driven D[15:0] by memory (ADDSET +1) (DATAST + 1) 2 HCLK HCLK cycles HCLK cycles cycles (ADDHLD + 1) HCLK cycles...
Page 422: Table 93. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0034 The differences with mode1 are the toggling of NADV, NOE that goes on toggling after NADV changes and the independent read and write timings. Table 93. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-15 0x0000 EXTMOD...
Page 423: Figure 173. Muxed Read Accesses
RM0034 Flexible static memory controller (FSMC) Mode muxed - asynchronous access muxed NOR Flash Figure 173. Muxed read accesses Memory transaction A[25:16] NADV High data driven AD[15:0] Lower address by memory 1HCLK cycle (ADDSET +1) (DATAST + 1) 2 HCLK (BUSTURN + 1) cycles HCLK cycles...
Page 424: Synchronous Burst Transactions
Flexible static memory controller (FSMC) RM0034 Table 96. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-15 0x0000 EXTMOD 13-10 WAITPOL Meaningful only if bit 15 is 1 BURSTEN FACCEN MWID As needed MTYP 0x2 (NOR) MUXEN MBKEN Table 97.
Page 425 RM0034 Flexible static memory controller (FSMC) Data latency versus NOR Flash latency The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR Flash configuration register.
Page 426: Table 98. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0034 Figure 175. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) Memory transaction = burst of 4 half words HCLK A[25:16] addr[25:16] High NADV NWAIT (WAITCFG = 0) NWAIT (WAITCFG = 1) DATALAT CLK cycles inserted wait state A/D[15:0] Addr[15:0]...
Page 427: Table 99. Fsmc_Tcrx Bit Fields
RM0034 Flexible static memory controller (FSMC) Table 98. FSMC_BCRx bit fields (continued) Bit No. Bit name Value to set WAITCFG to be set according to memory WRAPMOD to be set according to memory WAITPOL to be set according to memory BURSTEN FWPRLVL Set to protect memory from accidental write access...
Page 428: Figure 176. Synchronous Multiplexed Write Mode - Psram (Cram)
Flexible static memory controller (FSMC) RM0034 Figure 176. Synchronous multiplexed write mode - PSRAM (CRAM) Memory transaction = burst of 4 half words HCLK A[25:16] addr[25:16] Hi-Z NADV NWAIT (WAITCFG = 0) DATALAT CLK cycles inserted wait state A/D[15:0] Addr[15:0] data data data...
Page 429: Table 100. Fsmc_Bcrx Bit Fields
RM0034 Flexible static memory controller (FSMC) Table 100. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-20 0x0000 CBURSTRW 18-15 EXTMOD When high, the first data after latency period is taken as always WAITEN valid, regardless of the wait from memory value WREN no effect on synchronous read WAITCFG...
Page 430: Nor/Psram Controller Registers
Flexible static memory controller (FSMC) RM0034 19.5.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4) Address offset: 0xA000 0000 + 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DX This register contains the control information of each memory bank, used for SRAMs, ROMs and asynchronous or burst NOR Flash memories.
Page 431 RM0034 Flexible static memory controller (FSMC) Bit 10 WRAPMOD: Wrapped burst mode support. Defines whether the controller will or not split an AHB burst wrap access into two linear accesses. Valid only when accessing memories in burst mode 0: Direct wrapped burst is not enabled (default after reset), 1: Direct wrapped burst is enabled.
Page 432 Flexible static memory controller (FSMC) RM0034 SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) Address offset: 0xA000 0000 + 0x04 + 8 * (x – 1), x = 1..4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, ROMs and NOR Flash memories.
Page 433 RM0034 Flexible static memory controller (FSMC) Bits 15:8 DATAST: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 162 Figure 174), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 2 ×...
Page 434 Flexible static memory controller (FSMC) RM0034 SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) Address offset: 0xA000 0000 + 0x104 + 8 * (x – 1), x = 1...4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, ROMs and NOR Flash memories.
Page 435: Nand Flash/Pc Card Controller
RM0034 Flexible static memory controller (FSMC) Bits 7:4 ADDHLD: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 171 Figure 174), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses: 0000: Reserved 0001: ADDHLD phase duration = 2 ×...
Page 436: External Memory Interface Signals
Flexible static memory controller (FSMC) RM0034 Table 102. Programmable NAND/PC Card access parameters Parameter Function Access mode Unit Min. Max. Number of clock cycles (HCLK) Memory setup AHB clock cycle to set up the address before the Read/Write time (HCLK) command assertion Minimum duration (HCLK clock AHB clock cycle...
Page 437: Table 104. 16-Bit Nand Flash
RM0034 Flexible static memory controller (FSMC) 16-bit NAND Flash Table 104. 16-bit NAND Flash FSMC signal name Function A[17] NAND Flash address latch enable (ALE) signal A[16] NAND Flash command latch enable (CLE) signal D[15:0] 16-bit multiplexed, bidirectional address/data bus NCE[x] Chip select, x = 2, 3 NOE(= NRE)
Page 438: Nand Flash / Pc Card Supported Memories And Transactions
Flexible static memory controller (FSMC) RM0034 19.6.2 NAND Flash / PC Card supported memories and transactions Table 106 below shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND Flash / PC Card controller appear in gray.
Page 439: Nand Flash Operations
RM0034 Flexible static memory controller (FSMC) Figure 177. NAND/PC Card controller timing for common memory access HCLK A[25:0] NCEx High NREG, NIOW, NIOR MEMxSET + 1 MEMxWAIT + 1 MEMxHOLD + 1 NWE, MEMxHIZ + 1 write_data read_data Valid ai14732c 1.
Page 440: Nand Flash Pre-Wait Functionality
Flexible static memory controller (FSMC) RM0034 the start address for read operations. Using the attribute memory space makes it possible to use a different timing configuration of the FSMC, which can be used to implement the prewait functionality needed by some NAND Flash memories (see details in Section 19.6.5: NAND Flash pre-wait functionality on page 440).
Page 441: Error Correction Code Computation Ecc (Nand Flash)
RM0034 Flexible static memory controller (FSMC) When this functionality is needed, it can be guaranteed by programming the MEMHOLD value to meet the t timing, however any CPU read or write access to the NAND Flash then has the hold delay of (MEMHOLD + 1) HCLK cycles inserted from the rising edge of the NWE signal to the next access.
Page 442 Flexible static memory controller (FSMC) RM0034 Bits 19:17 ECCPS: ECC page size. Defines the page size for the extended ECC: 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes Bits 16:13 TAR: ALE to RE delay. Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
Page 443 RM0034 Flexible static memory controller (FSMC) FIFO status and interrupt register 2..4 (FSMC_SR2..4) Address offset: 0xA000 0000 + 0x44 + 0x20 * (x-1), x = 2..4 Reset value: 0x0000 0040 This register contains information about FIFO status and interrupt. The FSMC has a FIFO that is used when writing to memories to store up to16 words of data from the AHB.
Page 444 Flexible static memory controller (FSMC) RM0034 Common memory space timing register 2..4 (FSMC_PMEM2..4) Address offset: Address: 0xA000 0000 + 0x48 + 0x20 * (x – 1), x = 2..4 Reset value: 0xFCFC FCFC Each FSMC_PMEMx (x = 2..4) read/write register contains the timing information for PC Card or NAND Flash memory bank x, used for access to the common memory space of the 16-bit PC Card/CompactFlash, or to access the NAND Flash for command, address write access and data read/write access.
Page 445 RM0034 Flexible static memory controller (FSMC) Attribute memory space timing registers 2..4 (FSMC_PATT2..4) Address offset: 0xA000 0000 + 0x4C + 0x20 * (x – 1), x = 2..4 Reset value: 0xFCFC FCFC Each FSMC_PATTx (x = 2..4) read/write register contains the timing information for PC Card/CompactFlash or NAND Flash memory bank x.
Page 446 Flexible static memory controller (FSMC) RM0034 I/O space timing register 4 (FSMC_PIO4) Address offset: 0xA000 0000 + 0xB0 Reset value: 0xFCFCFCFC The FSMC_PIO4 read/write registers contain the timing information used to gain access to the I/O space of the 16-bit PC Card/CompactFlash. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 IOHIZx IOHOLDx...
Page 447: Fsmc Register Map
RM0034 Flexible static memory controller (FSMC) recorded in the spare area, to determine whether a page is valid, and, to correct it if applicable. The FSMC_ECCRx registers should be cleared after being read by setting the ECCEN bit to zero. For computing a new data block, the ECCEN bit must be set to one. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ECCx Bits 31:0 ECCx: ECC result...
Page 448 Flexible static memory controller (FSMC) RM0034 Table 108. FSMC register map (continued) Offset Register 0xA000 ACCM FSMC_BTR4 Res. DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 001C 0xA000 ACCM FSMC_BWTR1 Res. DATLAT CLKDIV Reserved DATAST ADDHLD ADDSET 0104 0xA000 ACCM FSMC_BWTR2 Res. DATLAT CLKDIV Reserved...
Page 449: Secure Digital Input/Output Interface (Sdio)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 450: Sdio Bus Topology
Secure digital input/output interface (SDIO) RM0034 The MultiMediaCard/SD bus connects cards to the controller. The current version of the SDIO supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. 20.2 SDIO bus topology Communication over the bus is based on command and data transfers.
Page 451: Figure 181. Sdio (Multiple) Block Write Operation
RM0034 Secure digital input/output interface (SDIO) Figure 181. SDIO (multiple) block write operation From host to card From card to host Stop command stops data transfer Data from host to card Command Response Command Response SDIO_CMD SDIO_D Busy Data block crc Data block crc Busy Busy...
Page 452: Sdio Functional Description
Secure digital input/output interface (SDIO) RM0034 20.3 SDIO functional description The SDIO consists of two parts: ● The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer. ●...
Page 453: Sdio Adapter
RM0034 Secure digital input/output interface (SDIO) Table 109. SDIO I/O definitions Direction Description MultiMediaCard/SD/SDIO card clock. This pin is the clock from SDIO_CK Output host to card. MultiMediaCard/SD/SDIO card command. This pin is the SDIO_CMD Bidirectional bidirectional command/response signal. MultiMediaCard/SD/SDIO card data. These pins are the SDIO_D[7:0] Bidirectional bidirectional databus.
Page 454: Figure 186. Control Unit
Secure digital input/output interface (SDIO) RM0034 Control unit The control unit contains the power management functions and the clock divider for the memory card clock. There are three power phases: ● power-off ● power-up ● power-on Figure 186. Control unit Control unit Power management Clock...
Page 455: Figure 187. Sdio Adapter Command Path
RM0034 Secure digital input/output interface (SDIO) Command path The command path unit sends commands to and receives responses from the cards. Figure 187. SDIO adapter command path Status Control Command To control unit flag logic timer Adapter registers SDIO_CMDin Argument SDIO_CMDout Shift register...
Page 456: Figure 188. Command Path State Machine (Cpsm)
Secure digital input/output interface (SDIO) RM0034 Figure 188. Command path state machine (CPSM) CE-ATA Command On reset Completion signal Wait_CPL received or CPSM disabled or Command CRC failed CPSM Enabled and Idle Response received or Response Received in CE-ATA pending command disabled or command mode and no interrupt and CRC failed...
Page 457: Table 110. Command Format
RM0034 Secure digital input/output interface (SDIO) Figure 189. SDIO command transfer at least 8 SDIO_CK cycles Command Response Command SDIO_CK State Idle Send Wait Receive Idle Send SDIO_CMD Hi-Z Controller drives Hi-Z Card drives Hi-Z Controller drives ai14707 ● Command format –...
Page 458: Table 111. Short Response Format
Secure digital input/output interface (SDIO) RM0034 Table 111. Short response format Bit position Width Value Description Start bit Transmission bit [45:40] Command index [39:8] Argument [7:1] CRC7(or 1111111) End bit Table 112. Long response format Bit position Width Value Description Start bit Transmission bit [133:128]...
Page 459: Figure 190. Data Path
RM0034 Secure digital input/output interface (SDIO) Data path The data path subunit transfers data to and from cards. Figure 190 shows a block diagram of the data path. Figure 190. Data path Data path Status Control Data To control unit flag logic timer...
Page 460: Figure 191. Data Path State Machine (Dpsm)
Secure digital input/output interface (SDIO) RM0034 Figure 191. Data path state machine (DPSM) On reset DPSM disabled DPSM enabled and Read Wait Read Wait Started and SD I/O mode enabled Disabled or FIFO underrun or Idle end of data or CRC fail Disabled or CRC fail or timeout Enable and not send...
Page 461: Table 114. Data Token Format
RM0034 Secure digital input/output interface (SDIO) Note: The DPSM remains in the Wait_S state for at least two clock periods to meet the N timing requirements, where N is the number of clock cycles between the reception of the card response and the start of the data transfer from the host.
Page 462: Table 115. Transmit Fifo Status Flags
Secure digital input/output interface (SDIO) RM0034 Depending on the TXACT and RXACT flags, the FIFO can be disabled, transmit enabled, or receive enabled. TXACT and RXACT are driven by the data path subunit and are mutually exclusive: – The transmit FIFO refers to the transmit logic and data buffer when TXACT is asserted –...
Page 463: Sdio Ahb Interface
RM0034 Secure digital input/output interface (SDIO) Table 116. Receive FIFO status flags Flag Description RXFIFOF Set to high when all 32 receive FIFO words contain valid data RXFIFOE Set to high when the receive FIFO does not contain valid data. Set to high when 8 or more receive FIFO words contain valid data.
Page 464: Card Functional Description
Secure digital input/output interface (SDIO) RM0034 Program the SDIO command register: CmdIndex with 24 (WRITE_BLOCK); WaitResp with ‘1’ (SDIO card host waits for a response); CPSMEN with ‘1’ (SDIO card host enabled to send a command). Other fields are at their reset value. Wait for SDIO_STA[6] = CMDREND interrupt, then program the SDIO data control register: DTEN with ‘1’...
Page 465: Card Identification Process
RM0034 Secure digital input/output interface (SDIO) 20.4.4 Card identification process The card identification process differs for MultiMediaCards and SD cards. For MultiMediaCard cards, the identification process starts at clock rate F . The SDIO_CMD line output drivers are open-drain and allow parallel card operation during this process. The registration process is accomplished as follows: The bus is activated.
Page 466: Block Write
Secure digital input/output interface (SDIO) RM0034 SDIO card host can reissue this command to change the RCA. The RCA of the card is the last assigned value. 20.4.5 Block write During block write (CMD24 - 27) one or more blocks of data are transferred from the host to the card with a CRC appended to the end of each block by the host.
Page 467: Stream Access, Stream Write And Stream Read (Multimediacard Only)
RM0034 Secure digital input/output interface (SDIO) If the host sends a stop transmission command after the card transmits the last block of a multiple block operation with a predefined number of blocks, it is responded to as an illegal command, since the card is no longer in the data state. If the host uses partial blocks whose accumulated length is not block-aligned and block misalignment is not allowed, the card detects a block misalignment error condition at the beginning of the first misaligned block (ADDRESS_ERROR error bit is set in the status register).
Page 468: Erase: Group Erase And Sector Erase
Secure digital input/output interface (SDIO) RM0034 The maximum clock frequency for a stream read operation is given by the following equation and uses fields of the card specific data register. 2 readbllen × ) NSAC – ( Maximumspeed MIN TRANSPEED ------------------------------------------------------------------------ ×...
Page 469: Protection Management
RM0034 Secure digital input/output interface (SDIO) 20.4.10 Protection management Three write protection methods for the cards are supported in the SDIO card host module: internal card write protection (card responsibility) mechanical write protection switch (SDIO card host module responsibility only) password-protected card lock operation Internal card write protection Card data can be protected against write and erase.
Page 470 Secure digital input/output interface (SDIO) RM0034 The bit settings are as follows: ● ERASE: setting it forces an erase operation. All other bits must be zero, and only the command byte is sent ● LOCK_UNLOCK: setting it locks the card. LOCK_UNLOCK can be set simultaneously with SET_PWD, however not with CLR_PWD ●...
Page 471 RM0034 Secure digital input/output interface (SDIO) Locking a card Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock mode (byte 0 in Table 130), the 8-bit PWD_LEN, and the number of bytes of the current password.
Page 472: Card Status Register
Secure digital input/output interface (SDIO) RM0034 Send LOCK/UNLOCK (CMD42) with the appropriate data byte on the data line including the 16-bit CRC. The data block indicates the mode (ERASE = 1). All other bits must be zero. When the ERASE bit is the only bit set in the data field, all card contents are erased, including the PWD and PWD_LEN fields, and the card is no longer locked.
Page 473: Table 117. Card Status
RM0034 Secure digital input/output interface (SDIO) Table 117. Card status Clear Bits Identifier Type Value Description condition The command address argument was out of the allowed range for this card. ’0’= no error ADDRESS_ A multiple block or stream read/write E R X OUT_OF_RANGE ’1’= error...
Page 474 Secure digital input/output interface (SDIO) RM0034 Table 117. Card status (continued) Clear Bits Identifier Type Value Description condition (Undefined by the standard) A generic ’0’= no error card error related to the (and detected ERROR ’1’= error during) execution of the last host command (e.g.
Page 475: Sd Status Register
RM0034 Secure digital input/output interface (SDIO) Table 117. Card status (continued) Clear Bits Identifier Type Value Description condition ’0’= no error Error in the sequence of the AKE_SEQ_ERROR ’1’= error authentication process Reserved for application specific commands Reserved for manufacturer test mode 20.4.12 SD status register The SD status contains status bits that are related to the SD memory card proprietary...
Page 476 Secure digital input/output interface (SDIO) RM0034 Table 118. SD status (continued) Clear Bits Identifier Type Value Description condition In the future, the 8 LSBs will ’00xxh’= SD Memory Cards as be used to define different defined in Physical Spec Ver1.01- variations of an SD memory 2.00 (’x’= don’t care).
Page 477: Table 119. Speed Class Code Field
RM0034 Secure digital input/output interface (SDIO) Table 119. Speed class code field SPEED_CLASS Value definition Class 0 Class 2 Class 4 Class 6 04h – FFh Reserved PERFORMANCE_MOVE This 8-bit field indicates Pm (performance move) and the value can be set by 1 [MB/sec] steps.
Page 478: Table 122. Maximum Au Size
Secure digital input/output interface (SDIO) RM0034 The maximum AU size, which depends on the card capacity, is defined in Table 122. The card can be set to any AU size between RU size and maximum AU size. Table 122. Maximum AU size Capacity 16 MB-64 MB 128 MB-256 MB...
Page 479: Sd I/O Mode
RM0034 Secure digital input/output interface (SDIO) ERASE_OFFSET This 2-bit field indicates T and one of four values can be selected. This field is OFFSET meaningless if the ERASE_SIZE and ERASE_TIMEOUT fields are set to 0. Table 125. Erase offset field ERASE_OFFSET Value definition 0 [sec]...
Page 480: Commands And Responses
Secure digital input/output interface (SDIO) RM0034 Waits for the completion of the higher priority transaction Restores the suspended transaction SD I/O ReadWait The optional ReadWait (RW) operation is defined only for the SD 1-bit and 4-bit modes. The ReadWait operation allows the MMC/SD module to signal a card that it is reading multiple registers (IO_RW_EXTENDED, CMD53) to temporarily stall the data transfer while allowing the MMC/SD module to send commands to any function within the SD I/O device.
Page 481: Table 126. Block-Oriented Write Commands
RM0034 Secure digital input/output interface (SDIO) Command types Both application-specific and general commands are divided into the four following types: ● broadcast command (BC): sent to all cards; no responses returned. ● broadcast command with response (BCR): sent to all cards; responses received from all cards simultaneously.
Page 482: Table 127. Block-Oriented Write Protection Commands
Secure digital input/output interface (SDIO) RM0034 Table 127. Block-oriented write protection commands Response Type Argument Abbreviation Description index format If the card has write protection features, this command sets the write protection bit [31:0] data CMD28 ac of the addressed group. The properties of SET_WRITE_PROT address write protection are coded in the card-...
Page 483: Response Formats
RM0034 Secure digital input/output interface (SDIO) Table 130. Lock card Response Type Argument Abbreviation Description index format Sets/resets the password or locks/unlocks CMD42 adtc [31:0] stuff bits the card. The size of the data block is set LOCK_UNLOCK by the SET_BLOCK_LEN command. CMD43 Reserved CMD54...
Page 484: R1B
Secure digital input/output interface (SDIO) RM0034 Table 132. R1 response Bit position Width (bits Value Description Start bit Transmission bit [45:40] Command index [39:8] Card status [7:1] CRC7 End bit 20.5.2 It is identical to R1 with an optional busy signal transmitted on the data line. The card may become busy after receiving these commands based on its state prior to the command reception.
Page 485: R4 (Fast I/O)
RM0034 Secure digital input/output interface (SDIO) Table 134. R3 response Bit position Width (bits Value Description Start bit Transmission bit [45:40] ‘111111’ Reserved [39:8] OCR register [7:1] ‘1111111’ Reserved End bit 20.5.5 R4 (Fast I/O) Code length: 48 bits. The argument field contains the RCA of the addressed card, the register address to be read out or written to, and its content.
Page 486: R5 (Interrupt Request)
Secure digital input/output interface (SDIO) RM0034 Table 136. R4b response (continued) Bit position Width (bits Value Description [7:1] Reserved End bit Once an SD I/O card has received a CMD5, the I/O portion of that card is enabled to respond normally to all further commands. This I/O enable of the function within the I/O card will remain set until a reset, power cycle or CMD52 with write to I/O reset is received by the card.
Page 487: Sdio I/O Card-Specific Operations
RM0034 Secure digital input/output interface (SDIO) Table 138. R6 response (continued) Bit position Width (bits) Value Description [7:1] CRC7 End bit The card [23:8] status bits are changed when CMD3 is sent to an I/O-only card. In this case, the 16 bits of response are the SD I/O-only values: ●...
Page 488: Sdio Suspend/Resume Operation
Secure digital input/output interface (SDIO) RM0034 20.6.3 SDIO suspend/resume operation While sending data to the card, the SDIO can suspend the write operation. the SDIO_CMD[11] bit is set and indicates to the CPSM that the current command is a suspend command.
Page 489: Ce-Ata Interrupt
RM0034 Secure digital input/output interface (SDIO) 20.7.3 CE-ATA interrupt The command completion is signaled to the CPU by the status bit SDIO_STA[23]. This static bit can be cleared with the clear bit SDIO_ICR[23]. The SDIO_STA[23] status bit can generate an interrupt on each interrupt line, depending on the mask bit SDIO_MASKx[23].
Page 490: Sdi Clock Control Register (Sdio_Clkcr)
Secure digital input/output interface (SDIO) RM0034 20.9.2 SDI clock control register (SDIO_CLKCR) Address offset: 0x04 Reset value: 0x0000 0000 The SDIO_CLKCR register controls the SDIO_CK output clock. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CLKDIV Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...
Page 491: Sdio Argument Register (Sdio_Arg)
RM0034 Secure digital input/output interface (SDIO) Note: While the SD/SDIO card or MultiMediaCard is in identification mode, the SDIO_CK frequency must be less than 400 kHz. The clock frequency can be changed to the maximum card bus frequency when relative card addresses are assigned to all cards.
Page 492: Sdio Command Response Register (Sdio_Respcmd)
Secure digital input/output interface (SDIO) RM0034 Bit 11 SDIOSuspend: SD I/O suspend command If this bit is set, the command to be sent is a suspend command (to be used only with SDIO card). Bit 10 CPSMEN: Command path state machine (CPSM) Enable bit If this bit is set, the CPSM is enabled.
Page 493: Sdio Response 1
RM0034 Secure digital input/output interface (SDIO) 20.9.6 SDIO response 1..4 register (SDIO_RESPx) Address offset: (0x10 + (4 × x)); x = 1..4 Reset value: 0x0000 0000 The SDIO_RESP1/2/3/4 registers contain the status of a card, which is part of the received response.
Page 494: Sdio Data Length Register (Sdio_Dlen)
Secure digital input/output interface (SDIO) RM0034 20.9.8 SDIO data length register (SDIO_DLEN) Address offset: 0x28 Reset value: 0x0000 0000 The SDIO_DLEN register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATALENGTH Reserved...
Page 495: Sdio Data Counter Register (Sdio_Dcount)
RM0034 Secure digital input/output interface (SDIO) Bits 7:4 DBLOCKSIZE: Data block size Define the data block length when the block data transfer mode is selected: 0000: (0 decimal) lock length = 2 = 1 byte 0001: (1 decimal) lock length = 2 = 2 bytes 0010: (2 decimal) lock length = 2 = 4 bytes...
Page 496: Sdio Status Register (Sdio_Sta)
Secure digital input/output interface (SDIO) RM0034 Bits 31:25 Reserved, always read as 0. Bits 24:0 DATACOUNT: Data count value When this bit is read, the number of remaining data bytes to be transferred is returned. Write has no effect. Note: This register should be read only when the data transfer is complete.
Page 497: Sdio Interrupt Clear Register (Sdio_Icr)
RM0034 Secure digital input/output interface (SDIO) Bit 9 STBITERR: Start bit not detected on all data signals in wide bus mode Bit 8 DATAEND: Data end (data counter, SDIDCOUNT, is zero) Bit 7 CMDSENT: Command sent (no response required) Bit 6 CMDREND: Command response received (CRC check passed) Bit 5 RXOVERR: Received FIFO overrun error Bit 4 TXUNDERR: Transmit FIFO underrun error Bit 3 DTIMEOUT: Data timeout...
Page 498 Secure digital input/output interface (SDIO) RM0034 Bit 8 DATAENDC: DATAEND flag clear bit Set by software to clear the DATAEND flag. 0: DATAEND not cleared 1: DATAEND cleared Bit 7 CMDSENTC: CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 0: CMDSENT not cleared 1: CMDSENT cleared Bit 6 CMDRENDC: CMDREND flag clear bit...
Page 499: Sdio Mask Register (Sdio_Mask)
RM0034 Secure digital input/output interface (SDIO) 20.9.13 SDIO mask register (SDIO_MASK) Address offset: 0x3C Reset value: 0x0000 0000 The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24...
Page 500 Secure digital input/output interface (SDIO) RM0034 Bit 16 TXFIFOFIE: Tx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO full. 0: Tx FIFO full interrupt disabled 1: Tx FIFO full interrupt enabled Bit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full.
Page 501: Sdio Fifo Counter Register (Sdio_Fifocnt)
RM0034 Secure digital input/output interface (SDIO) Bit 6 CMDRENDIE: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 0: Command response received interrupt disabled 1: command Response Received interrupt enabled Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.
Page 502: Sdio Data Fifo Register (Sdio_Fifo)
Secure digital input/output interface (SDIO) RM0034 20.9.15 SDIO data FIFO register (SDIO_FIFO) Address offset: 0x80 Reset value: 0x0000 0000 The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
Page 503 RM0034 Secure digital input/output interface (SDIO) Table 140. SDIO register map (continued) Offset Register 0x38 SDIO_ICR 0x3C SDIO_MASK 0x48 SDIO_FIFOCNT Reserved FIFOCOUNT 0x80 SDIO_FIFO FIF0Data Note: Refer to Table 1 on page 40 for the register boundary addresses. 503/959...
Page 504: Universal Serial Bus Full-Speed Device Interface (Usb)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 505: Figure 192. Usb Peripheral Block Diagram
RM0034 Universal serial bus full-speed device interface (USB) Figure 192. USB peripheral block diagram USB clock (48 MHz) Analog transceiver PCLK1 Control Clock RX-TX registers & logic recovery Suspend timer Control Endpoint Interrupt selection registers & logic S.I.E. Packet buffer Endpoint Endpoint interface...
Page 506: Description Of Usb Blocks
Universal serial bus full-speed device interface (USB) RM0034 proper handshake packet over the USB is generated or expected according to the direction of the transfer. At the end of the transaction, an endpoint-specific interrupt is generated, reading status registers and/or using different interrupt response routines. The microcontroller can determine: ●...
Page 507: Programming Considerations
RM0034 Universal serial bus full-speed device interface (USB) ● Control Registers: These are the registers containing information about the status of the whole USB peripheral and used to force some USB events, such as resume and power-down. ● Interrupt Registers: These contain the Interrupt masks and a record of the events. They can be used to inquire an interrupt reason, the interrupt status or to clear the status of a pending interrupt.
Page 508: System And Power-On Reset
Universal serial bus full-speed device interface (USB) RM0034 21.4.2 System and power-on reset Upon system and power-on reset, the first operation the application software should perform is to provide all required clock signals to the USB peripheral and subsequently de-assert its reset signal so to be able to access its registers.
Page 509 RM0034 Universal serial bus full-speed device interface (USB) clock is fixed by the requirements of the USB standard at 48 MHz, and this can be different from the clock used for the interface to the APB1 bus. Different clock configurations are possible where the APB1 clock frequency can be higher or lower than the USB peripheral one.
Page 510: Figure 193. Packet Buffer Areas With Examples Of Buffer Description Table Locations
Universal serial bus full-speed device interface (USB) RM0034 Figure 193. Packet buffer areas with examples of buffer description table locations Buffer for double-buffered IN Endpoint 3 0001_1110 (1E) COUNT3_TX_1 0001_1100 (1C) ADDR3_TX_1 0001_1010 (1A) COUNT3_TX_0 Buffer for double-buffered 0001_1000 (18) ADDR3_TX_0 OUT Endpoint 2 0001_0110 (16)
Page 511 RM0034 Universal serial bus full-speed device interface (USB) NUM_BLOCK fields. Unidirectional endpoints, except Isochronous and double-buffered bulk endpoints, need to initialize only bits and registers related to the supported direction. Once the transmission and/or reception are enabled, register USB_EPnR and locations ADDRn_TX/ADDRn_RX, COUNTn_TX/COUNTn_RX (respectively), should not be modified by the application software, as the hardware can change their value on the fly.
Page 512 Universal serial bus full-speed device interface (USB) RM0034 software). Data bytes subsequently received by the USB peripheral are packed in words (the first byte received is stored as least significant byte) and then transferred to the packet buffer starting from the address contained in the internal ADDR register while BUF_COUNT is decremented and COUNT is incremented at each byte transfer.
Page 513 RM0034 Universal serial bus full-speed device interface (USB) OUT transactions from SETUP ones. A USB device can determine the number and direction of data stages by interpreting the data transferred in the SETUP stage, and is required to STALL the transaction in the case of errors. To do so, at all data stages before the last, the unused direction should be set to STALL, so that, if the host reverses the transfer direction too soon, it gets a STALL as a status stage.
Page 514: Double-Buffered Endpoints
Universal serial bus full-speed device interface (USB) RM0034 21.4.3 Double-buffered endpoints All different endpoint types defined by the USB standard represent different traffic models, and describe the typical requirements of different kind of data transfer operations. When large portions of data are to be transferred between the host PC and the USB function, the bulk endpoint type is the most suited model.
Page 515: Table 141. Double-Buffering Buffer Flag Definition
RM0034 Universal serial bus full-speed device interface (USB) Table 141. Double-buffering buffer flag definition Buffer flag ‘Transmission’ endpoint ‘Reception’ endpoint DTOG DTOG_TX (USB_EPnRbit 6) DTOG_RX (USB_EPnRbit 14) SW_BUF USB_EPnR bit 14 USB_EPnR bit 6 The memory buffer which is currently being used by the USB peripheral is defined by DTOG buffer flag, while the buffer currently in use by application software is identified by SW_BUF buffer flag.
Page 516: Isochronous Transfers
Universal serial bus full-speed device interface (USB) RM0034 remains ‘11’ (Valid). However, as the token packet of a new transaction is received, the actual endpoint status will be masked as ‘10’ (NAK) when a buffer conflict between the USB peripheral and the application software is detected (this condition is identified by DTOG and SW_BUF having the same value, see Table 142 on page 515).
Page 517: Suspend/Resume Events
RM0034 Universal serial bus full-speed device interface (USB) Table 143. Isochronous memory buffers usage Endpoint DTOG bit Packet buffer used by the Packet buffer used by the Type value USB peripheral application software ADDRn_TX_0 / COUNTn_TX_0 ADDRn_TX_1 / COUNTn_TX_1 buffer description table buffer description table locations.
Page 518: Table 144. Resume Event Detection
Universal serial bus full-speed device interface (USB) RM0034 A brief description of a typical suspend procedure is provided below, focused on the USB- related aspects of the application software routine responding to the SUSP notification of the USB peripheral: Set the FSUSP bit in the USB_CNTR register to 1. This action activates the suspend mode within the USB peripheral.
Page 519: Usb Registers
RM0034 Universal serial bus full-speed device interface (USB) In this case, the resume sequence can be started by setting the RESUME bit in the USB_CNTR register to ‘1’ and resetting it to 0 after an interval between 1mS and 15mS (this interval can be timed using ESOF interrupts, occurring with a 1mS period when the system clock is running at nominal frequency).
Page 520 Universal serial bus full-speed device interface (USB) RM0034 Bit 15 CTRM: Correct transfer interrupt mask 0: Correct Transfer (CTR) Interrupt disabled. 1: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. Bit 14 PMAOVRM: Packet memory area over / underrun interrupt mask 0: PMAOVR Interrupt disabled.
Page 521 RM0034 Universal serial bus full-speed device interface (USB) Bit 2 LP_MODE: Low-power mode This mode is used when the suspend-mode power constraints require that all static power dissipation is avoided, except the one required to supply the external pull-up resistor. This condition should be entered when the application is ready to stop all system clocks, or reduce their frequency in order to meet the power consumption requirements of the USB suspend condition.
Page 522 Universal serial bus full-speed device interface (USB) RM0034 The user can choose the relative priority of simultaneously pending USB_ISTR events by specifying the order in which software checks USB_ISTR bits in an interrupt service routine. Only the bits related to events, which are serviced, are cleared. At the end of the service routine, another interrupt will be requested, to service the remaining conditions.
Page 523 RM0034 Universal serial bus full-speed device interface (USB) Bit 11 SUSP: Suspend mode request This bit is set by the hardware when no traffic has been received for 3mS, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (FSUSP=1) until the end of resume sequence.
Page 524 Universal serial bus full-speed device interface (USB) RM0034 Bits 3:0 EP_ID[3:0]: Endpoint Identifier These bits are written by the hardware according to the endpoint number, which generated the interrupt request. If several endpoint transactions are pending, the hardware writes the endpoint identifier related to the endpoint having the highest priority defined in the following way: Two endpoint sets are defined, in order of priority: Isochronous and double-buffered bulk endpoints are considered first and then the other endpoints are examined.
Page 525 RM0034 Universal serial bus full-speed device interface (USB) USB device address (USB_DADDR) Address offset: 0x4C Reset value: 0x0000 Reserved ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Res. Bits 15:8 Reserved Bit 7 EF: Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD[6:0] bits.
Page 526: Endpoint-Specific Registers
Universal serial bus full-speed device interface (USB) RM0034 21.5.2 Endpoint-specific registers The number of these registers varies according to the number of endpoints that the USB peripheral is designed to handle. The USB peripheral supports up to 8 bidirectional endpoints. Each USB device must support a control endpoint whose address (EA bits) must be set to 0.
Page 527 RM0034 Universal serial bus full-speed device interface (USB) Bit 14 DTOG_RX: Data Toggle, for reception transfers If the endpoint is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent to the USB host, following a data packet reception having a matching data PID value;...
Page 528 Universal serial bus full-speed device interface (USB) RM0034 Bit 8 EP_KIND: Endpoint kind The meaning of this bit depends on the endpoint type configured by the EP_TYPE bits. Table 147 summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint.
Page 529: Buffer Descriptor Table
RM0034 Universal serial bus full-speed device interface (USB) Bits 3:0 EA[3:0]: Endpoint address Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Table 145.
Page 530 Universal serial bus full-speed device interface (USB) RM0034 and buffer description table locations. In the following pages two location addresses are reported: the one to be used by application software while accessing the packet memory, and the local one relative to USB Peripheral access.
Page 531 RM0034 Universal serial bus full-speed device interface (USB) COUNTn_TX_1[9:0] COUNTn_TX_0[9:0] Reception buffer address n (USB_ADDRn_RX) Address offset: [USB_BTABLE] + n*16 + 8 USB local Address: [USB_BTABLE] + n*8 + 4 ADDRn_RX[15:1] Bits 15:1 ADDRn_RX[15:1]: Reception buffer address These bits point to the starting address of the packet buffer, which will contain the data received by the endpoint associated with the USB_EPnR register at the next OUT/SETUP token addressed to it.
Page 532: Table 149. Definition Of Allocated Buffer Memory
Universal serial bus full-speed device interface (USB) RM0034 Bit 15 BL_SIZE: BLock size This bit selects the size of memory block used to define the allocated buffer area. – If BL_SIZE=0, the memory block is 2 byte large, which is the minimum block allowed in a word-wide memory.
Page 533: Usb Register Map
RM0034 Universal serial bus full-speed device interface (USB) 21.5.4 USB register map The table below provides the USB register map and reset values. Table 150. USB register map and reset values Offset Register STAT_ STAT_ USB_EP0R TYPE EA[3:0] 0x00 Reserved [1:0] [1:0] [1:0]...
Page 534 Universal serial bus full-speed device interface (USB) RM0034 Table 150. USB register map and reset values (continued) Offset Register USB_BTABLE BTABLE[15:3] 0x50 Reserved Reserved Reset value Note: Refer to Table 1 on page 40 for the register boundary addresses. 534/959...
Page 535: Controller Area Network (Bxcan)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 536: Bxcan General Description
Controller area network (bxCAN) RM0034 Management ● Maskable interrupts ● Software-efficient mailbox mapping at a unique address space Dual CAN (connectivity line only) ● CAN1: Master bxCAN for managing the communication between a Slave bxCAN and the 512-byte SRAM memory ●...
Page 537: Can 2.0B Active Core
RM0034 Controller area network (bxCAN) 22.3.1 CAN 2.0B active core The bxCAN module handles the transmission and the reception of CAN messages fully autonomously. Standard identifiers (11-bit) and extended identifiers (29-bit) are fully supported by hardware. 22.3.2 Control, status and configuration registers The application uses these registers to: ●...
Page 538: Figure 195. Can General Block Diagram
Controller area network (bxCAN) RM0034 Figure 195. CAN general block diagram Tx Mailboxes Receive FIFO 0 Receive FIFO 1 Mailbox 2 Master Control Mailbox 0 Mailbox 0 Master Status Mailbox 1 Tx Status Rx FIFO 0 Status Rx FIFO 1 Status Mailbox 0 Interrupt Enable Error Status...
Page 539: Bxcan Operating Modes
RM0034 Controller area network (bxCAN) Figure 196. Dual CAN block diagram (connectivity devices) CAN1 (Master) with 512 bytes SRAM Master Tx Mailboxes Master Master Receive FIFO 0 Receive FIFO 1 Mailbox 0 Mailbox 0 Mailbox 0 Master Control Master Status Tx Status Rx FIFO 0 Status Transmission...
Page 540: Initialization Mode
Controller area network (bxCAN) RM0034 mode. Before entering normal mode bxCAN always has to synchronize on the CAN bus. To synchronize, bxCAN waits until the CAN bus is idle, this means 11 consecutive recessive bits have been monitored on CANRX. 22.4.1 Initialization mode The software initialization can be done while the hardware is in Initialization mode.
Page 541: Test Mode
RM0034 Controller area network (bxCAN) bxCAN can be woken up (exit Sleep mode) either by software clearing the SLEEP bit or on detection of CAN bus activity. On CAN bus activity detection, hardware automatically performs the wakeup sequence by clearing the SLEEP bit if the AWUM bit in the CAN_MCR register is set. If the AWUM bit is cleared, software has to clear the SLEEP bit when a wakeup interrupt occurs, in order to exit from Sleep mode.
Page 542: Loop Back Mode
Controller area network (bxCAN) RM0034 remain in recessive state. Silent mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits (Acknowledge Bits, Error Frames). Figure 198. bxCAN in silent mode bxCAN CANTX CANRX 22.5.2...
Page 543: Stm32F10Xxx In Debug Mode
RM0034 Controller area network (bxCAN) Figure 200. bxCAN in combined mode bxCAN CANTX CANRX 22.6 STM32F10xxx in Debug mode When the microcontroller enters the debug mode (Cortex-M3 core halted), the bxCAN continues to work normally or stops, depending on: ● the DBG_CAN1_STOP bit for CAN1 or the DBG_CAN2_STOP bit for CAN2 in the DBG module.
Page 544: Figure 201. Transmit Mailbox States
Controller area network (bxCAN) RM0034 The transmit mailboxes can be configured as a transmit FIFO by setting the TXFP bit in the CAN_MCR register. In this mode the priority order is given by the transmit request order. This mode is very useful for segmented transmission. Abort A transmission request can be aborted by the user setting the ABRQ bit in the CAN_TSR register.
Page 545: Time Triggered Communication Mode
RM0034 Controller area network (bxCAN) 22.7.2 Time triggered communication mode In this mode, the internal counter of the CAN hardware is activated and used to generate the Time Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx and Tx mailboxes). The internal counter is incremented each CAN bit time (refer to Section 22.7.7: Bit timing).
Page 546: Identifier Filtering
Controller area network (bxCAN) RM0034 FIFO management Starting from the empty state, the first valid message received is stored in the FIFO which becomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the CAN_RFR register to the value 01b. The message is available in the FIFO output mailbox. The software reads out the mailbox content and releases it by setting the RFOM bit in the CAN_RFR register.
Page 547 RM0034 Controller area network (bxCAN) resources which would be otherwise needed to perform filtering by software. Each filter bank x consists of two 32-bit registers, CAN_FxR0 and CAN_FxR1. Scalable width To optimize and adapt the filters to the application needs, each filter bank can be scaled independently.
Page 548: Figure 203. Filter Bank Scale Configuration - Register Organization
Controller area network (bxCAN) RM0034 Figure 203. Filter bank scale configuration - register organization Filter Num. One 32-Bit Filter - Identifier Mask CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8] CAN_FxR1[7:0] Mask CAN_FxR2[31:24] CAN_FxR2[23:16] CAN_FxR2[15:8] CAN_FxR2[7:0] Mapping STID[10:3] STID[2:0] EXID[17:13] EXID[12:5] EXID[4:0] Two 32-Bit Filters - Identifier List CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8]...
Page 549: Figure 204. Example Of Filter Numbering
RM0034 Controller area network (bxCAN) Figure 204. Example of filter numbering Filter Filter Filter Filter FIFO0 FIFO1 Bank Num. Bank Num. ID List (32-bit) ID Mask (16-bit) ID Mask (32-bit) ID List (32-bit) Deactivated ID List (16-bit) ID Mask (16-bit) Deactivated ID Mask (16-bit) ID List (32-bit)
Page 550: Message Storage
Controller area network (bxCAN) RM0034 Figure 205. Filtering mechanism - example Example of 3 filter banks in 32-bit Unidentified List mode and the remaining in 32-bit Identifier Mask mode Message Received Identifier Data Ctrl Filter bank Receive FIFO Identifier Identifier Message Stored Identifier...
Page 551: Table 151. Transmit Mailbox Mapping
RM0034 Controller area network (bxCAN) Table 151. Transmit mailbox mapping Offset to transmit mailbox base Register name address CAN_TIxR CAN_TDTxR CAN_TDLxR CAN_TDHxR Receive mailbox When a message has been received, it is available to the software in the FIFO output mailbox.
Page 552: Error Management
Controller area network (bxCAN) RM0034 22.7.6 Error management The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error Counter (TEC value, in CAN_ESR register) and a Receive Error Counter (REC value, in the CAN_ESR register), which get incremented or decremented according to the error condition.
Page 553: Figure 207. Bit Timing
RM0034 Controller area network (bxCAN) A valid edge is defined as the first transition in a bit time from dominant to recessive bus level provided the controller itself does not send a recessive bit. If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so that the sample point is delayed.
Page 554: Bxcan Interrupts
Controller area network (bxCAN) RM0034 Figure 208. CAN frames Inter-Frame Space Inter-Frame Space Data Frame (Standard identifier) or Overload Frame 44 + 8 * N Ctrl Field Data Field CRC Field Ack Field Arbitration Field 8 * N Inter-Frame Space Inter-Frame Space Data Frame (Extended Identifier) or Overload Frame...
Page 555: Figure 209. Event Flags And Interrupt Generation
RM0034 Controller area network (bxCAN) Figure 209. Event flags and interrupt generation CAN_IER TRANSMIT INTERRUPT TMEIE RQCP0 & CAN_TSR RQCP1 RQCP2 FMPIE0 & FIFO 0 FMP0 INTERRUPT FFIE0 & CAN_RF0R FULL0 FOVIE0 & FOVR0 FMPIE1 & FIFO 1 FMP1 INTERRUPT FFIE1 &...
Page 556: Can Registers
Controller area network (bxCAN) RM0034 ● The error and status change interrupt can be generated by the following events: – Error condition, for more details on error conditions please refer to the CAN Error Status register (CAN_ESR). – Wakeup condition, SOF monitored on the CAN Rx signal. –...
Page 557 RM0034 Controller area network (bxCAN) Bits 14:8 Reserved, forced by hardware to 0. Bit 7 TTCM: Time triggered communication mode 0: Time Triggered Communication mode disabled. 1: Time Triggered Communication mode enabled Note: For more information on Time Triggered Communication mode, please refer to Section 22.7.2: Time triggered communication mode.
Page 558 Controller area network (bxCAN) RM0034 Bit 0 INRQ Initialization request The software clears this bit to switch the hardware into normal mode. Once 11 consecutive recessive bits have been monitored on the Rx signal the CAN hardware is synchronized and ready for transmission and reception.
Page 559 RM0034 Controller area network (bxCAN) Bit 2 ERRI Error interrupt This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and the corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status change interrupt if the ERRIE bit in the CAN_IER register is set.
Page 560 Controller area network (bxCAN) RM0034 Bit 27 TME1 Transmit mailbox 1 empty This bit is set by hardware when no transmit request is pending for mailbox 1. Bit 26 TME0 Transmit mailbox 0 empty This bit is set by hardware when no transmit request is pending for mailbox 0. Bits 25:24 CODE[1:0] Mailbox code In case at least one transmit mailbox is free, the code value is equal to the number of the...
Page 561 RM0034 Controller area network (bxCAN) Bit 8 RQCP1 Request completed mailbox1 Set by hardware when the last request (transmit or abort) has been performed. Cleared by software writing a “1” or by hardware on transmission request (TXRQ1 set in CAN_TI1R register). Clearing this bit clears all the status bits (TXOK1, ALST1 and TERR1) for Mailbox 1.
Page 562 Controller area network (bxCAN) RM0034 Bit 3 FULL0 FIFO 0 full Set by hardware when three messages are stored in the FIFO. This bit is cleared by software. Bit 2 Reserved, forced by hardware to 0. Bits 1:0 FMP0[1:0] FIFO 0 message pending These bits indicate how many messages are pending in the receive FIFO.
Page 563 RM0034 Controller area network (bxCAN) CAN interrupt enable register (CAN_IER) Address offset: 0x14 Reset value: 0x00 SLKIE WKUIE Reserved ERRIE Reserved Res. Bits 31:18 Reserved, forced by hardware to 0. Bit 17 SLKIE Sleep interrupt enable 0: No interrupt when SLAKI bit is set. 1: Interrupt generated when SLAKI bit is set.
Page 564 Controller area network (bxCAN) RM0034 Bit 3 FOVIE0 FIFO overrun interrupt enable 0: No interrupt when FOVR bit is set. 1: Interrupt generated when FOVR bit is set. Bit 2 FFIE0 FIFO full interrupt enable 0: No interrupt when FULL bit is set. 1: Interrupt generated when FULL bit is set.
Page 565 RM0034 Controller area network (bxCAN) Bit 2 BOFF Bus-off flag This bit is set by hardware when it enters the bus-off state. The bus-off state is entered on TEC overflow, greater than 255, refer to Section 22.7.6 on page 552. Bit 1 EPVF: Error passive flag This bit is set by hardware when the Error Passive limit has been reached (Receive Error Counter or Transmit Error Counter>127).
Page 566: Mailbox Registers
Controller area network (bxCAN) RM0034 22.9.3 Mailbox registers This chapter describes the registers of the transmit and receive mailboxes. Refer to Section 22.7.5: Message storage on page 550 for detailed register mapping. Transmit and receive mailboxes have the same registers except: ●...
Page 567 RM0034 Controller area network (bxCAN) Bit 1 RTR Remote transmission request 0: Data frame 1: Remote frame Bit 0 TXRQ Transmit mailbox request Set by software to request the transmission for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. Mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2) All bits of this register are write protected when the mailbox is not in empty state.
Page 568 Controller area network (bxCAN) RM0034 Mailbox data low register (CAN_TDLxR) (x=0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x188, 0x198, 0x1A8 Reset value: undefined DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] Bits 31:24 DATA3[7:0] Data byte 3 Data byte 3 of the message.
Page 569 RM0034 Controller area network (bxCAN) Rx FIFO mailbox identifier register (CAN_RIxR) (x=0..1) Address offsets: 0x1B0, 0x1C0 Reset value: undefined Note: All RX registers are write protected. STID[10:0]/EXID[28:18] EXID[17:13] EXID[12:0] Res. Bits 31:21 STID[10:0]/EXID[28:18] Standard identifier or extended identifier The standard identifier or the MSBs of the extended identifier (depending on the IDE bit value).
Page 570 Controller area network (bxCAN) RM0034 Bits 31:16 TIME[15:0] Message time stamp This field contains the 16-bit timer value captured at the SOF detection. Bits 15:8 FMI[7:0] Filter match index This register contains the index of the filter the message stored in the mailbox passed through.
Page 571: Can Filter Registers
RM0034 Controller area network (bxCAN) Receive FIFO mailbox data high register (CAN_RDHxR) (x=0..1) Address offsets: 0x1BC, 0x1CC Reset value: undefined Note: All RX registers are write protected. DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] Bits 31:24 DATA7[7:0] Data Byte 7 Data byte 3 of the message. Bits 23:16 DATA6[7:0] Data Byte 6 Data byte 2 of the message.
Page 572 Controller area network (bxCAN) RM0034 Bits 13:8 CAN2SB[5:0] CAN2 start bank These bits are set and cleared by software. They define the start bank for the CAN2 interface (Slave) in the range 1 to 27. Note: These bits are available in connectivity line devices only and are reserved otherwise. Bits 7:1 Reserved, forced to reset value Bit 0 FINIT...
Page 573 RM0034 Controller area network (bxCAN) Note: Please refer to Figure 203: Filter bank scale configuration - register organization on page 548 Bits 31:28 Reserved, forced by hardware to 0. Bits 27:0 FSCx Filter scale configuration These bits define the scale configuration of Filters 13-0. 0: Dual 16-bit scale configuration 1: Single 32-bit scale configuration Note: Bits 27:14 are available in connectivity line devices only and are reserved otherwise.
Page 574 Controller area network (bxCAN) RM0034 Bits 31:28 Reserved, forced by hardware to 0. Bits 27:0 FACTx Filter active The software sets this bit to activate Filter x. To modify the Filter x registers (CAN_FxR[0:7]), the FACTx bit must be cleared or the FINIT bit of the CAN_FMR register must be set. 0: Filter x is not active 1: Filter x is active Note: Bits 27:14 are available in connectivity line devices only and are reserved otherwise.
Page 575: Bxcan Register Map
RM0034 Controller area network (bxCAN) 22.9.5 bxCAN register map Refer to Table 1 on page 40 for the register boundary addresses. In connectivity line devices, the registers at offset 0x200 to 31C are present only in CAN1. Table 153. bxCAN register map and reset values Offset Register CAN_MCR...
Page 576 Controller area network (bxCAN) RM0034 Table 153. bxCAN register map and reset values (continued) Offset Register CAN_TDT1R TIME[15:0] DLC[3:0] 0x194 Reserved Reserved Reset value CAN_TDL1R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 0x198 Reset value CAN_TDH1R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 0x19C Reset value CAN_TI2R STID[10:0]/EXID[28:18] EXID[17:0]...
Page 577 RM0034 Controller area network (bxCAN) Table 153. bxCAN register map and reset values (continued) Offset Register CAN_FMR CAN2SB[5:0] 0x200 Reserved Reserved Reset value CAN_FM1R FBM[27:0] 0x204 Reserved Reset value 0x208 Reserved CAN_FS1R FSC[27:0] 0x20C Reserved Reset value 0x210 Reserved CAN_FFA1R FFA[27:0] 0x214 Reserved...
Page 578: Serial Peripheral Interface (Spi)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 579: Spi And I S Main Features
RM0034 Serial peripheral interface (SPI) 23.2 SPI and I S main features 23.2.1 SPI features ● Full-duplex synchronous transfers on three lines ● Simplex synchronous transfers on two lines with or without a bidirectional data line ● 8- or 16-bit transfer frame format selection ●...
Page 580: I 2 S Features
Serial peripheral interface (SPI) RM0034 23.2.2 S features ● Simplex communication (only transmitter or receiver) ● Master or slave operations ● 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 96 kHz) ● Data format may be 16-bit, 24-bit or 32-bit ●...
Page 581: Spi Functional Description
RM0034 Serial peripheral interface (SPI) 23.3 SPI functional description 23.3.1 General description The block diagram of the SPI is shown in Figure 210. Figure 210. SPI block diagram Address and data bus Read Rx buffer SPI_CR2 MOSI RXNE TXDM RXDM SSOE Shift register MISO...
Page 582: Figure 211. Single Master/ Single Slave Application
Serial peripheral interface (SPI) RM0034 Figure 211. Single master/ single slave application Master Slave MSBit LSBit MSBit LSBit MISO MISO 8-bit shift register 8-bit shift register MOSI MOSI SPI clock generator Not used if NSS is managed by software ai14745 1.
Page 583 RM0034 Serial peripheral interface (SPI) Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the SPI_CR1 register. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred.
Page 584: Figure 213. Data Clock Timing Diagram
Serial peripheral interface (SPI) RM0034 Figure 213. Data clock timing diagram CPHA =1 CPOL = 1 CPOL = 0 MISO LSBit MSBit (from master) 8 or 16 bits depending on Data Frame Format (see SPI_CR1) MOSI LSBit MSBit (from slave) (to slave) Capture strobe CPHA =0...
Page 585: Spi Slave Mode
RM0034 Serial peripheral interface (SPI) 23.3.2 SPI slave mode In slave configuration, the serial clock is received on the SCK pin from the master device. The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data transfer rate.
Page 586: Simplex Communication
Serial peripheral interface (SPI) RM0034 Procedure Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register). Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 213).
Page 587: Status Flags
RM0034 Serial peripheral interface (SPI) 1 clock and 1 data wire (receive-only in full-duplex mode) In order to free an I/O pin so it can be used for other purposes, it is possible to disable the SPI output function by setting the RXONLY bit in the SPI_CR1 register. In this case, SPI will function in Receive-only mode.
Page 588: Spi Communication Using Dma (Direct Memory Addressing)
Serial peripheral interface (SPI) RM0034 Note: This SPI offers two kinds of CRC calculation standard which depend directly on the data frame format selected for the transmission and/or reception: 8-bit data (CR8) and 16-bit data (CRC16-CCITT). CRC calculation is enabled by setting the CRCEN bit in the SPI_CR1 register. This action resets the CRC registers (SPI_RXCRCR and SPI_TXCRCR).
Page 589: Error Flags
RM0034 Serial peripheral interface (SPI) DMA capability with CRC When SPI communication is enabled with the CRC communication and the DMA mode, the transmission and reception of the CRC bytes at the end of communication are done automatically. At the end of data and CRC transfers, the CRCERR flag in SPI_SR is set if corruption occurs during the transfer.
Page 590: Disabling The Spi
Serial peripheral interface (SPI) RM0034 received in the shift register (after transmission of the transmitter SPI_TXCRCR value) does not match the receiver SPI_RXCRCR value. 23.3.9 Disabling the SPI When transfer is terminated, the application can stop the communication by disabling the SPI peripheral.
Page 591: Figure 214. I 2 S Block Diagram
RM0034 Serial peripheral interface (SPI) Figure 214. I S block diagram Address and data bus Tx buffer BSY OVR MODF CRC TxE RxNE SIDE 16-bit MOSI/ SD Shift register MISO LSB first Communication 16-bit control Rx buffer NSS/WS I2SCFG I2SSTD CKPOL DATLEN [1:0]...
Page 592: Supported Audio Protocols
Serial peripheral interface (SPI) RM0034 An additional pin could be used when a master clock output is needed for some external audio devices: ● MCK: Master Clock (mapped separately) is used, when the I S is configured in master mode (and when the MCKOE bit in the SPI_I2SPR register is set), to output this additional clock generated at a preconfigured frequency rate equal to 256 ×...
Page 593: Figure 215. I 2 S Phillips Protocol Waveforms (16/32-Bit Full Accuracy, Cpol = 0)
RM0034 Serial peripheral interface (SPI) Figure 215. I S Phillips protocol waveforms (16/32-bit full accuracy, CPOL = 0) Transmission Reception May be 16-bit, 32-bit LSB MSB Channel left Channel right Data are latched on the falling edge of CK (for the transmitter) and are read on the rising edge (for the receiver).
Page 594: Figure 218. Receiving 0X8Eaa33
Serial peripheral interface (SPI) RM0034 ● In reception mode: if data 0x8EAA33 is received: Figure 218. Receiving 0x8EAA33 Second read from Data register First read from Data register 0x8EAA 0x3300 Only the 8MSB are right The 8 LSB will always be 00 Figure 219.
Page 595: Figure 221. Msb Justified 16-Bit Or 32-Bit Full-Accuracy Length With Cpol = 0
RM0034 Serial peripheral interface (SPI) MSB justified standard For this standard, the WS signal is generated at the same time as the first data bit, which is the MSBit. Figure 221. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 Transmission Reception May be 16-bit, 32-bit...
Page 596: Figure 224. Lsb Justified 16-Bit Or 32-Bit Full-Accuracy With Cpol = 0
Serial peripheral interface (SPI) RM0034 LSB justified standard This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit full-accuracy frame formats). Figure 224. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 Transmission Reception May be 16-bit, 32-bit LSB MSB...
Page 597: Figure 227. Operations Required To Receive 0X3478Ae
RM0034 Serial peripheral interface (SPI) Figure 227. Operations required to receive 0x3478AE Second read from Data register First read from Data register conditioned by RXNE = ‘1’ conditioned by RXNE = ‘1’ 0x0034 0x78AE Only the 8 LSB bits of the half-word are significant.
Page 598: Figure 230. Pcm Standard Waveforms (16-Bit)
Serial peripheral interface (SPI) RM0034 PCM standard For the PCM standard, there is no need to use channel-side information. The two PCM modes (short and long frame) are available and configurable using the PCMSYNC bit in SPI_I2SCFGR. Figure 230. PCM standard waveforms (16-bit) short frame up to 13-bit...
Page 599: Clock Generator
RM0034 Serial peripheral interface (SPI) 23.4.3 Clock generator The I S bitrate determines the dataflow on the I S data line and the I S clock signal frequency. S bitrate = number of bits per channel × number of channels × sampling audio frequency For a 16-bit audio, left and right channel, the I S bitrate is calculated as follows: S bitrate = 16 ×...
Page 600: Table 155. Audio-Frequency Precision Using Standard 8 Mhz Hse
Serial peripheral interface (SPI) RM0034 When the master clock is generated (MCKOE in the SPI_I2SPR register is set): = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide When the master clock is disabled (MCKOE bit cleared): = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide...
Page 601: Table 156. Audio-Frequency Precision Using Standard 25 Mhz And Pll3
RM0034 Serial peripheral interface (SPI) Table 156. Audio-frequency precision using standard 25 MHz and PLL3 (connectivity line devices only) PREDIV2 PLL3 I2SDIV I2SODD Real F (kHz) Error Target MCLK (Hz) 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 96000 95942.98 95942.98 0.0594% 0.0594%...
Page 602: I 2 S Master Mode
Serial peripheral interface (SPI) RM0034 Table 157. Audio-frequency precision using standard 14.7456 MHz and PLL3 (connectivity line devices only) PREDIV2 PLL3 I2SDIV I2SODD Real F (kHz) Error Target MCLK (Hz) 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 96000...
Page 603 RM0034 Serial peripheral interface (SPI) Select also the I S master mode and direction (Transmitter or Receiver) through the I2SCFG[1:0] bits in the SPI_I2SCFGR register. If needed, select all the potential interruption sources and the DMA capabilities by writing the SPI_CR2 register. The I2SE bit in SPI_I2SCFGR register must be set.
Page 604: I 2 S Slave Mode
Serial peripheral interface (SPI) RM0034 To switch off the I S in reception mode, I2SE has to be cleared during and before the end of the last data reception. Even if I2SE is switched off while the last data are being transferred, the clock and the transfer are maintained until the end of the current data transmission.
Page 605: Status Flags
RM0034 Serial peripheral interface (SPI) Reception sequence The operating mode is the same as for the transmission mode except for the point 1. where the configuration should set the master reception mode using the I2SCFG[1:0] bits in the SPI_I2SCFGR register. Whatever the data length or the channel length, the audio data are received by 16-bit packets.
Page 606: Error Flags
Serial peripheral interface (SPI) RM0034 Channel Side flag (CHSIDE) In transmission mode, this flag is refreshed when TXE goes high. It indicates the channel side to which the data to transfer on SD has to belong. In case of an underrun error event in slave transmission mode, this flag is not reliable and I S needs to be switched off and switched on before resuming the communication.
Page 607: Dma Features
RM0034 Serial peripheral interface (SPI) 23.4.9 DMA features DMA is working in exactly the same way as for the SPI mode. There is no difference on the S. Only the CRC feature is not available in I S mode since there is no data transfer protection system.
Page 608 Serial peripheral interface (SPI) RM0034 Bit 10 RXONLY: Receive only This bit combined with the BIDImode bit selects the direction of transfer in 2-line unidirectional mode. This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted.
Page 609: Spi Control Register 2 (Spi_Cr2)
RM0034 Serial peripheral interface (SPI) Bit 2 MSTR: Master selection 0: Slave configuration 1: Master configuration Note: This bit should not be changed when communication is ongoing. Not used in I S mode Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing.
Page 610: Spi Status Register (Spi_Sr)
Serial peripheral interface (SPI) RM0034 Bit 2 SSOE: SS output enable 0: SS output is disabled in master mode and the cell can work in multimaster configuration 1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work in a multimaster environment.
Page 611: Spi Data Register (Spi_Dr)
RM0034 Serial peripheral interface (SPI) Bit 3 UDR: Underrun flag 0: No underrun occurred 1: Underrun occurred This flag is set by hardware and reset by a software sequence. Refer to Section 23.4.7 on page 606 for the software sequence. Note: Not used in SPI mode Bit 2 CHSIDE: Channel side 0: Channel Left has to be transmitted or has been received...
Page 612: Spi Crc Polynomial Register (Spi_Crcpr)
Serial peripheral interface (SPI) RM0034 23.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I mode) Address offset: 0x10 Reset value: 0x0007 CRCPOLY[15:0] Bits 15:0 CRCPOLY[15:0]: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required.
Page 613: Spi Tx Crc Register (Spi_Txcrcr)
RM0034 Serial peripheral interface (SPI) 23.5.7 SPI Tx CRC register (SPI_TXCRCR) (not used in I S mode) Address offset: 0x18 Reset value: 0x0000 TxCRC[15:0] Bits 15:0 TxCRC[15:0]: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes.
Page 614 Serial peripheral interface (SPI) RM0034 Bit 7 PCMSYNC: PCM frame synchronization 0: Short frame synchronization 1: Long frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used) Not used for the SPI mode Bit 6 Reserved: forced at 0 by hardware Bit 5:4 I2SSTD: I2S standard selection 00: I...
Page 615: Spi_I 2 S Prescaler Register (Spi_I2Spr)
RM0034 Serial peripheral interface (SPI) 23.5.9 SPI_I S prescaler register (SPI_I2SPR) Address offset: 20h Reset value: 0000 0010 (0002h) Reserved MCKOE I2SDIV Res. Bits 15:10 Reserved: Forced to 0 by hardware Bit 9 MCKOE: Master clock output enable 0: Master clock output is disabled 1: Master clock output is enabled Note: This bit should be configured when the I S is disabled.
Page 616: Spi Register Map
Serial peripheral interface (SPI) RM0034 23.5.10 SPI register map The table provides shows the SPI register map and reset values. Table 159. SPI register map and reset values Offset Register SPI_CR1 BR [2:0] 0x00 Reserved Reset Value SPI_CR2 0x04 Reserved Reset Value SPI_SR 0x08...
Page 617: Inter-Integrated Circuit (I 2 C) Interface
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 618: I 2 C Functional Description
Inter-integrated circuit (I C) interface RM0034 – Arbitration lost condition for master mode – Acknowledgement failure after address/ data transmission – Detection of misplaced start or stop condition – Overrun/Underrun if clock stretching is disabled ● 2 Interrupt vectors: – 1 Interrupt for successful address/ data communication –...
Page 619: Figure 234. I2C Bus Protocol
RM0034 Inter-integrated circuit (I C) interface Communication flow In Master mode, the I C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software.
Page 620: I2C Slave Mode
Inter-integrated circuit (I C) interface RM0034 Figure 235. I C block diagram DATA REGISTER DATA DATA SHIFT REGISTER CONTROL PEC CALCULATION COMPARATOR OWN ADDRESS REGISTER DUAL ADDRESS REGISTER CLOCK PEC REGISTER CONTROL CLOCK CONTROL REGISTER (CCR) CONTROL REGISTERS (CR1&CR2) CONTROL STATUS REGISTERS LOGIC (SR1&SR2)
Page 621: Figure 236. Transfer Sequence Diagram For Slave Transmitter
RM0034 Inter-integrated circuit (I C) interface Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set and waits for the 8-bit slave address. Address matched: the interface generates in sequence: ● An acknowledge pulse if the ACK bit is set ●...
Page 622: Figure 237. Transfer Sequence Diagram For Slave Receiver
Inter-integrated circuit (I C) interface RM0034 Slave receiver Following the address reception and after clearing ADDR, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: ●...
Page 623: I2C Master Mode
RM0034 Inter-integrated circuit (I C) interface 24.3.3 C master mode In Master mode, the I C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a Start condition and ends with a Stop condition. Master mode is selected as soon as the Start condition is generated on the bus with a START bit.
Page 624 Inter-integrated circuit (I C) interface RM0034 Slave address transmission Then the slave address is sent to the SDA line via the internal shift register. ● In 10-bit addressing mode, sending the header sequence causes the following event: – The ADD10 bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.
Page 625: Figure 238. Transfer Sequence Diagram For Master Transmitter
RM0034 Inter-integrated circuit (I C) interface Closing the communication After writing the last byte to the DR register, the STOP bit is set by software to generate a Stop condition (see Figure 238 Transfer sequencing EV8_2). The interface goes automatically back to slave mode (M/SL bit cleared). Note: Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set.
Page 626: Error Conditions
Inter-integrated circuit (I C) interface RM0034 Closing the communication The master sends a NACK for the last byte received from the slave. After receiving this NACK, the slave releases the control of the SCL and SDA lines. Then the master can send a Stop/Re-Start condition.
Page 627 RM0034 Inter-integrated circuit (I C) interface Bus error (BERR) This error occurs when the I C interface detects a Stop or a Start condition during a byte transfer. In this case, ● The BERR bit is set and an interrupt is generated if the ITERREN bit is set ●...
Page 628: Sda/Scl Line Control
Inter-integrated circuit (I C) interface RM0034 24.3.5 SDA/SCL line control ● If clock stretching is enabled: – Transmitter mode: If TxE=1 and BTF=1: the interface holds the clock line low before transmission to wait for the microcontroller to read SR1 and then write the byte in the Data Register (both buffer and shift register are empty).
Page 629 RM0034 Inter-integrated circuit (I C) interface Table 160. SMBus vs. I C (continued) SMBus 7-bit, 10-bit and general call slave address Different address types (reserved, dynamic etc.) types Different bus protocols (quick command, process No bus protocols call etc.) SMBus application usage With System Management Bus, a device can provide manufacturer information, tell the system what its model/part number is, save its state for a suspend event, report different types of errors, accept control parameters, and return its status.
Page 630: Dma Requests
Inter-integrated circuit (I C) interface RM0034 A slave-only device can signal the host through SMBALERT that it wants to talk by setting ALERT bit in I2C_CR1 register. The host processes the interrupt and simultaneously accesses all SMBALERT devices through the Alert Response Address (known as ARA having a value 0001 100X).
Page 631 RM0034 Inter-integrated circuit (I C) interface corresponding DMA channel is reached, the DMA controller sends an End of Transfer EOT signal to the I C interface and generates a Transfer Complete interrupt if enabled: ● Master transmitter: In the interrupt routine after the EOT interrupt, disable DMA requests then wait for a BTF event before programming the Stop condition.
Page 632: Packet Error Checking
Inter-integrated circuit (I C) interface RM0034 When the number of data transfers which has been programmed in the DMA Controller registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the C interface and DMA generates an interrupt, if enabled, on the DMA channel interrupt vector.
Page 633: I 2 C Debug Mode
RM0034 Inter-integrated circuit (I C) interface Table 161. I C Interrupt requests (continued) Interrupt event Event flag Enable Control bit Bus error BERR Arbitration loss (Master) ARLO Acknowledge failure Overrun/Underrun ITERREN PEC error PECERR Timeout/Tlow error TIMEOUT SMBus Alert SMBALERT Note: SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically ORed on the same interrupt channel.
Page 634: I 2 C Registers
Inter-integrated circuit (I C) interface RM0034 DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, refer to Section 30.15.2: Debug support for timers, watchdog, bxCAN and I C on page 945. 24.6 C registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions.
Page 635 RM0034 Inter-integrated circuit (I C) interface Bit 10 ACK: Acknowledge enable This bit is set and cleared by software and cleared by hardware when PE=0. 0: No acknowledge returned 1: Acknowledge returned after a byte is received (matched address or data) Bit 9 STOP: Stop generation The bit is set and cleared by software, cleared by hardware when a Stop condition is detected, set by hardware when a timeout error is detected.
Page 636: Control Register 2 (I2C_Cr2)
Inter-integrated circuit (I C) interface RM0034 Bit 0 PE: Peripheral enable 0: Peripheral disable 1: Peripheral enable: the corresponding I/Os are selected as alternate functions depending on SMBus bit. Note: If this bit is reset while a communication is on going, the peripheral is disabled at the end of the current communication, when back to IDLE state.
Page 637: Own Address Register 1 (I2C_Oar1)
RM0034 Inter-integrated circuit (I C) interface Bit 8 ITERREN: Error interrupt enable 0: Error interrupt disabled 1: Error interrupt enabled This interrupt is generated when: – BERR = 1 – ARLO = 1 – AF = 1 – OVR = 1 –...
Page 638: Own Address Register 2 (I2C_Oar2)
Inter-integrated circuit (I C) interface RM0034 24.6.4 Own address register 2 (I2C_OAR2) Address offset: 0x0C Reset value: 0x0000 ADD2[7:1] ENDUAL Reserved Bits 15:8 Reserved, forced by hardware to 0. Bits 7:1 ADD2[7:1]: Interface address bits 7:1 of address in dual addressing mode Bit 0 ENDUAL: Dual addressing mode enable 0: Only OAR1 is recognized in 7-bit addressing mode 1: Both OAR1 and OAR2 are recognized in 7-bit addressing mode...
Page 639: Status Register 1 (I2C_Sr1)
RM0034 Inter-integrated circuit (I C) interface 24.6.6 Status register 1 (I2C_SR1) Address offset: 0x14 Reset value: 0x0000 TIME STOP ARLO BERR RxNE ADD10 ADDR ALERT Res. Res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bit 15 SMBALERT: SMBus alert In SMBus host mode: 0: no SMBAlert 1: SMBAlert event occurred on pin In SMBus slave mode:...
Page 640 Inter-integrated circuit (I C) interface RM0034 Bit 10 AF: Acknowledge failure 0: No acknowledge failure 1: Acknowledge failure – Set by hardware when no acknowledge is returned. – Cleared by software writing 0, or by hardware when PE=0. Bit 9 ARLO: Arbitration lost (master mode) 0: No Arbitration Lost detected 1: Arbitration Lost detected Set by hardware when the interface loses the arbitration of the bus to another master...
Page 641 RM0034 Inter-integrated circuit (I C) interface Bit 3 ADD10: 10-bit header sent (Master mode) 0: No ADD10 event occurred. 1: Master has sent first address byte (header). – Set by hardware when the master has sent the first byte in 10-bit address mode. –...
Page 642: Status Register 2 (I2C_Sr2)
Inter-integrated circuit (I C) interface RM0034 24.6.7 Status register 2 (I2C_SR2) Address offset: 0x18 Reset value:0x0000 PEC[7:0] DUALF Res. BUSY HOST CALL AULT Bits 15:8 PEC[7:0] Packet error checking register This register contains the internal PEC when ENPEC=1. Bit 7 DUALF: Dual flag (Slave mode) 0: Received address matched with OAR1 1: Received address matched with OAR2 –...
Page 643: Clock Control Register (I2C_Ccr)
RM0034 Inter-integrated circuit (I C) interface Bit 2 TRA: Transmitter/receiver 0: Data bytes received 1: Data bytes transmitted This bit is set depending on the R/W bit of the address byte, at the end of total address phase. It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.
Page 644: Trise Register (I2C_Trise)
Inter-integrated circuit (I C) interface RM0034 Bits 11:0 CCR[11:0]: Clock control register in Fast/Standard mode (Master mode) Controls the SCL clock in master mode. Standard mode or SMBus: = CCR * T high PCLK1 = CCR * T PCLK1 Fast mode: If DUTY = 0: = CCR * T high...
Page 645: I2C Register Map
RM0034 Inter-integrated circuit (I C) interface 24.6.10 C register map The table below provides the I C register map and reset values. Table 162. I C register map and reset values Offset Register I2C_CR1 0x00 Reserved Reset value I2C_CR2 FREQ[5:0] 0x04 Reserved Reset value...
Page 646: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 647: Usart Functional Description
RM0034 Universal synchronous asynchronous receiver transmitter (USART) – 0.5, 1.5 Stop Bits for Smartcard operation ● Single wire Half Duplex Communication ● Configurable multibuffer communication using DMA (direct memory access) – Buffering of received/transmitted bytes in reserved SRAM using centralized DMA ●...
Page 648 Universal synchronous asynchronous receiver transmitter (USART) RM0034 Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: ● An Idle Line prior to transmission or reception ● A start bit ● A data word (8 or 9 bits) least significant bit first ●...
Page 649: Figure 241. Usart Block Diagram
RM0034 Universal synchronous asynchronous receiver transmitter (USART) Figure 241. USART block diagram PRDATA PWDATA Write Read (DATA REGISTER) DR (CPU or DMA) (CPU or DMA) Receive Data Register (RDR) Transmit Data Register (TDR) IrDA SW_RX ENDEC Receive Shift Register Transmit Shift Register BLOCK IRDA_OUT IRDA_IN...
Page 650: Usart Character Description
Universal synchronous asynchronous receiver transmitter (USART) RM0034 25.3.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 242). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data (The number of “1”...
Page 651: Transmitter
RM0034 Universal synchronous asynchronous receiver transmitter (USART) 25.3.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the SCLK pin.
Page 652: Figure 243. Configurable Stop Bits
Universal synchronous asynchronous receiver transmitter (USART) RM0034 Figure 243. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next Data Frame Parity Data Frame Next Start Start Stop Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse a) 1 Stop Bit Possible...
Page 653: Receiver
RM0034 Universal synchronous asynchronous receiver transmitter (USART) When no transmission is taking place, a write instruction to the USART_DR register places the data directly in the shift register, the data transmission starts, and the TXE bit is immediately set. When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt is generated if the TCIE is set in the USART_CR1 register.
Page 654: Figure 244. Start Bit Detection
Universal synchronous asynchronous receiver transmitter (USART) RM0034 Figure 244. Start bit detection RX state Idle Start bit RX line Ideal sample 10 11 12 13 14 15 16 clock sampled values Real 10 11 12 13 14 15 16 sample clock 6/16 7/16...
Page 655 RM0034 Universal synchronous asynchronous receiver transmitter (USART) When a character is received ● The RXNE bit is set. It indicates that the content of the shift register is transferred to the RDR. In other words, data has been received and can be read (as well as its associated error flags).
Page 656: Table 163. Noise Detection From Sampled Data
Universal synchronous asynchronous receiver transmitter (USART) RM0034 when the new data is received during the reading sequence (between the USART_SR register read access and the USART_DR read access). Noise error Over-sampling techniques are used (except in synchronous mode) for data recovery by discriminating between valid incoming data and noise.
Page 657: Fractional Baud Rate Generation
RM0034 Universal synchronous asynchronous receiver transmitter (USART) When the framing error is detected: ● The FE bit is set by hardware ● The invalid data is transferred from the Shift register to the USART_DR register. ● No interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit which itself generates an interrupt.
Page 658: Table 164. Error Calculation For Programmed Baud Rates
Universal synchronous asynchronous receiver transmitter (USART) RM0034 Fraction (USARTDIV) = 12/16 = 0.75d Therefore USARTDIV = 27.75d Example 2: To program USARTDIV = 25.62d, This leads to: DIV_Fraction = 16*0.62d = 9.92d, nearest real number 10d = 0xA DIV_Mantissa = mantissa (25.620d) = 25d = 0x19 Then, USART_BRR = 0x19A Example 3: To program USARTDIV = 50.99d...
Page 659: Multiprocessor Communication
RM0034 Universal synchronous asynchronous receiver transmitter (USART) 25.3.5 Multiprocessor communication There is a possibility of performing multiprocessor communication with the USART (several USARTs connected in a network). For instance one of the USARTs can be the master, its TX output is connected to the RX input of the other USART. The others are slaves, their respective TX outputs are logically ANDed together and connected to the RX input of the master.
Page 660: Parity Control
Universal synchronous asynchronous receiver transmitter (USART) RM0034 The USART enters mute mode when an address character is received which does not match its programmed address. The RXNE flag is not set for this address byte and no interrupt nor DMA request is issued as the USART would have entered mute mode. It exits from mute mode when an address character is received which matches the programmed address.
Page 661: Lin (Local Interconnection Network) Mode
RM0034 Universal synchronous asynchronous receiver transmitter (USART) Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit in USART_CR1 = 1). Transmission mode: If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of “1s”...
Page 662: Figure 248. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
Universal synchronous asynchronous receiver transmitter (USART) RM0034 Figure 248. Break detection in LIN mode (11-bit break length - LBDL bit is set) Case 1: break signal not long enough => break discarded, LBD is not set ‚ÄúShort‚Äù Break F RX line Capture Strobe Break State machine Idle...
Page 663: Usart Synchronous Mode
RM0034 Universal synchronous asynchronous receiver transmitter (USART) Figure 249. Break detection in LIN mode vs. Framing error detection In these examples, we suppose that LBDL=1 (11-bit break length), M=0 (8-bit data) Case 1: break occurring after an Idle RX line data 1 IDLE BREAK...
Page 664: Figure 250. Usart Example Of Synchronous Transmission
Universal synchronous asynchronous receiver transmitter (USART) RM0034 has been written). This means that it is not possible to receive a synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly.
Page 665: Single Wire Half Duplex Communication
RM0034 Universal synchronous asynchronous receiver transmitter (USART) Figure 252. USART data clock timing diagram (M=1) Idle or preceding Start transmission M=1 (9 data bits) Idle or next Stop transmission Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1) Data on TX (from master) MSB Stop...
Page 666: Smartcard
Universal synchronous asynchronous receiver transmitter (USART) RM0034 arbiter, for instance). In particular, the transmission is never blocked by hardware and continue to occur as soon as a data is written in the data register while the TE bit is set. 25.3.10 Smartcard The Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register.
Page 667: Figure 255. Parity Error Detection Using The 1.5 Stop Bits
RM0034 Universal synchronous asynchronous receiver transmitter (USART) NACK signal (pulling transmit line low for 1 baud clock) will cause a framing error on the transmitter side (configured with 1.5 stop bits). The application can handle re-sending of data according to the protocol. A parity error is ‘NACK’ed by the receiver if the NACK control bit is set, otherwise a NACK is not transmitted.
Page 668: Irda Sir Endec Block
Universal synchronous asynchronous receiver transmitter (USART) RM0034 25.3.11 IrDA SIR ENDEC block The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared: ● LINEN, STOP and CLKEN bits in the USART_CR2 register, ●...
Page 669: Continuous Communication Using Dma
RM0034 Universal synchronous asynchronous receiver transmitter (USART) Receiver: Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the USART should discard pulses of duration shorter than 1/PSC. A valid low is accepted only if its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in USART_GTPR).
Page 670 Universal synchronous asynchronous receiver transmitter (USART) RM0034 Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to the DMA specification) to the USART_DR register whenever the TXE bit is set.
Page 671: Hardware Flow Control
RM0034 Universal synchronous asynchronous receiver transmitter (USART) case of single byte reception, there will be separate error flag interrupt enable bit (EIE bit in the USART_CR3 register), which if set will issue an interrupt after the current byte with either of these errors. 25.3.13 Hardware flow control It is possible to control the serial data flow between 2 devices by using the nCTS input and...
Page 672: Usart Interrupts
Universal synchronous asynchronous receiver transmitter (USART) RM0034 When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the nCTS input toggles. It indicates when the receiver becomes ready or not ready for communication. An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. The figure below shows an example of communication with CTS flow control enabled.
Page 673: Usart Mode Configuration
RM0034 Universal synchronous asynchronous receiver transmitter (USART) Figure 261. USART interrupt mapping diagram TCIE TXEIE CTSIE USART IDLE interrupt IDLEIE RXNEIE RXNEIE RXNE PEIE LBDIE DMAR 25.5 USART mode configuration Table 167. USART mode configuration USART modes USART1 USART2 USART3 UART4 UART5 Asynchronous mode...
Page 674: Status Register (Usart_Sr)
Universal synchronous asynchronous receiver transmitter (USART) RM0034 25.6.1 Status register (USART_SR) Address offset: 0x00 Reset value: 0x00C0 Reserved Reserved RXNE IDLE Res. rc_w0 rc_w0 rc_w0 rc_w0 Bits 31:10 Reserved, forced by hardware to 0. Bit 9 CTS: CTS flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software (by writing it to 0).
Page 675 RM0034 Universal synchronous asynchronous receiver transmitter (USART) Bit 4 IDLE: IDLE line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the IDLEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the USART_SR register followed by a read to the USART_DR register).
Page 676: Data Register (Usart_Dr)
Universal synchronous asynchronous receiver transmitter (USART) RM0034 25.6.2 Data register (USART_DR) Address offset: 0x04 Reset value: Undefined Reserved Reserved DR[8:0] Res. Bits 31:9 Reserved, forced by hardware to 0. Bits 8:0 DR[8:0]: Data value Contains the Received or Transmitted data character, depending on whether it is read from or written to.
Page 677: Control Register 1 (Usart_Cr1)
RM0034 Universal synchronous asynchronous receiver transmitter (USART) 25.6.4 Control register 1 (USART_CR1) Address offset: 0x0C Reset value: 0x0000 Reserved RXNE Reserved WAKE PEIE TXEIE TCIE IDLEIE Res. Bits 31:14 Reserved, forced by hardware to 0. Bit 13 UE: USART enable When this bit is cleared the USART prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.
Page 678 Universal synchronous asynchronous receiver transmitter (USART) RM0034 Bit 6 TCIE: Transmission complete interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An USART interrupt is generated whenever TC=1 in the USART_SR register Bit 5 RXNEIE: RXNE interrupt enable This bit is set and cleared by software.
Page 679: Control Register 2 (Usart_Cr2)
RM0034 Universal synchronous asynchronous receiver transmitter (USART) 25.6.5 Control register 2 (USART_CR2) Address offset: 0x10 Reset value: 0x0000 Reserved LINEN STOP[1:0] CPOL CPHA LBCL Res. LBDIE LBDL Res. ADD[3:0] Res. Bits 31:15 Reserved, forced by hardware to 0. Bit 14 LINEN: LIN mode enable This bit is set and cleared by software.
Page 680: Control Register 3 (Usart_Cr3)
Universal synchronous asynchronous receiver transmitter (USART) RM0034 Bit 8 LBCL: Last bit clock pulse This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the SCLK pin 1: The clock pulse of the last data bit is output to the SCLK pin Note: 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected...
Page 681 RM0034 Universal synchronous asynchronous receiver transmitter (USART) Bit 9 CTSE: CTS enable 0: CTS hardware flow control disabled 1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while a data is being transmitted, then the transmission is completed before stopping.
Page 682: Guard Time And Prescaler Register (Usart_Gtpr)
Universal synchronous asynchronous receiver transmitter (USART) RM0034 Bit 0 EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise error (FE=1 or ORE=1 or NE=1 in the USART_SR register) in case of Multi Buffer Communication (DMAR=1 in the USART_CR3 register).
Page 683: Usart Register Map
RM0034 Universal synchronous asynchronous receiver transmitter (USART) 25.6.8 USART register map The table below gives the USART register map and reset values. Table 168. USART register map and reset values Offset Register USART_SR 0x00 Reserved Reset value USART_DR DR[8:0] 0x04 Reserved Reset value DIV_Fraction...
Page 684: Usb On-The-Go Full-Speed (Otg_Fs)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 685: General Features
RM0034 USB on-the-go full-speed (OTG_FS) 26.2.1 General features The OTG_FS interface: complies with the Universal Serial Bus Specification, Revision 2.0 complies with the USB On-The-Go Supplement, Revision 1.3 is software-configurable to operate as: – USB FS/LS host – USB FS device –...
Page 686: Device-Mode Features
USB on-the-go full-speed (OTG_FS) RM0034 26.2.3 Device-mode features: The OTG_FS interface: has 1 bidirectional control endpoint0 has 3 IN endpoints (EP) configurable to support any kind of Bulk, Interrupt or Isochronous transfer has 3 OUT endpoints configurable to support any kind of Bulk, Interrupt or Isochronous transfer manages a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of SPRAM space manages up to 4 dedicated Tx-IN FIFOs (one for each IN-configured EP) to put less...
Page 687: Device Architecture
RM0034 USB on-the-go full-speed (OTG_FS) 26.3.2 Device architecture In Device mode, the core is configured to have individual dedicated FIFOs for each IN endpoint. The dedicated transmit FIFO architecture is a more flexible architecture that puts less load on the application. There are no request queues associated with any of the FIFOs. There is no need for the application to predict the order in which the USB host is going to access the nonperiodic endpoints.
Page 688: Figure 264. Bius Address Map
USB on-the-go full-speed (OTG_FS) RM0034 AHB slave bus interface unit (BIUS) The AHB slave interface unit converts AHB cycles to CSR write/read, Data-FIFO read/write, and DFIFO push/pop signals. Figure 264 shows the address map of the AHB slave bus interface unit. Figure 264.
Page 689: Figure 265. Host-Mode Fifo Address Mapping And Ahb Fifo Access Mapping
RM0034 USB on-the-go full-speed (OTG_FS) Within the controller: Read access to any one of the 4 KB regions is mapped to the RxFIFO Write operations to any non-periodic IN endpoint or OUT channel are mapped to the non-periodic TxFIFO In Host mode, write operations to any periodic OUT channel are mapped to the common periodic TxFIFO In Device mode, write access to one of the IN endpoints is mapped to the corresponding endpoint Tx FIFO (bits 30:27 in the Device endpoint control register map...
Page 690: Figure 266. Device-Mode Fifo Address Mapping And Ahb Fifo Access Mapping
USB on-the-go full-speed (OTG_FS) RM0034 Figure 266. Device-mode FIFO address mapping and AHB FIFO access mapping Single data FIFO DIEPTXF2[31:16] IN endpoint Tx FIFO #n Dedicated Tx Tx FIFO #n DFIFO push access packet FIFO #n control DIEPTXFx[15:0] from AHB (optional) MAC pop DIEPTXF2[15:0]...
Page 691: Figure 267. Mac Components
RM0034 USB on-the-go full-speed (OTG_FS) The AIU is responsible for the following functions: Generating and writing the delimiter (byte enables and last DWORD indicator) into the transmit FIFOs (based on FIFO number) for transmit packets in Device (IN) and Host (OUT) modes Writing a token into the request queue (periodic/non-periodic) for transmit transactions in Device and Host modes...
Page 692 USB on-the-go full-speed (OTG_FS) RM0034 The major blocks are: Device speed enumeration, suspend, and resume block (DSSR) The DSSR block is only active in Device mode. This block performs the speed enumeration, suspend, resume and remote wakeup functions in Device mode. Parallel interface engine (PIE): this block is responsible for token, data, and handshake packet generation and reception, and PID and CRC checking and generation.
Page 693: Sof Trigger
RM0034 USB on-the-go full-speed (OTG_FS) resume signaling from the host, initiates remote wakeup, handles soft connect and disconnect, decodes and tracks SOF packets, and handles high-speed test modes. Host protocol handling In Host mode, the MAC detects the device connect and disconnect, handles the USB reset and speed enumeration process, initiates USB suspend and resume, detects remote wakeup, generates SOF packets, and handles high-speed test modes.
Page 694: Figure 269. Interrupt Hierarchy
USB on-the-go full-speed (OTG_FS) RM0034 Figure 269. Interrupt hierarchy Interrupt Global interrupt mask (Bit 0) AHB configuration register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17:10 2 1 0 Core interrupt mask Core interrupt register register interrupt...
Page 695: Otg_Fs Control And Status Registers
RM0034 USB on-the-go full-speed (OTG_FS) 26.6 OTG_FS control and status registers By reading from and writing to the control and status registers (CSRs) through the AHB slave interface, the application controls the OTG_FS controller. These registers are 32 bits wide, and the addresses are 32-bit block aligned. CSRs are classified as follows: Core global registers Host-mode registers Host global registers...
Page 696: Table 169. Core Global Control And Status Registers (Csrs)
USB on-the-go full-speed (OTG_FS) RM0034 Figure 270. CSR memory map 0000h Core global CSRs (1 Kbyte) 0400h Host mode CSRs (1 Kbyte) 0800h Device mode CSRs (1.5 Kbyte) 0E00h Power and clock gating CSRs (0.5 Kbyte) 1000h Device EP 0/Host channel 0 FIFO (4 Kbyte) 2000h Device EP1/Host channel 1 FIFO (4 Kbyte) 3000h...
Page 697: Table 170. Host-Mode Control And Status Registers (Csrs)
RM0034 USB on-the-go full-speed (OTG_FS) Table 169. Core global control and status registers (CSRs) (continued) Address Acronym Register name offset OTG_FS_GRXSTSR 0x01C OTG_FS Receive status debug read/OTG status read and pop registers (OTG_FS_GRXSTSR/OTG_FS_GRXSTSP) on page 715 OTG_FS_GRXSTSP 0x020 OTG_FS_GRXFSIZ 0x024 OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) on page 716 OTG_FS non-periodic transmit FIFO size register (OTG_FS_GNPTXFSIZ) OTG_FS_GNPTXFSIZ...
Page 698: Table 171. Device-Mode Control And Status Registers
USB on-the-go full-speed (OTG_FS) RM0034 Table 170. Host-mode control and status registers (CSRs) (continued) Offset Acronym Register name address 0x500 0x520 OTG_FS host channel-x characteristics register (OTG_FS_HCCHARx) OTG_FS_HCCHARx (x = 0..7, where x = Channel_number) on page 726 0x6E0h OTG_FS host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, OTG_FS_HCINTx 508h where x = Channel_number) on page 727...
Page 699 RM0034 USB on-the-go full-speed (OTG_FS) Table 171. Device-mode control and status registers (continued) Offset Acronym Register name address 0x920 0x940 OTG device endpoint-x control register (OTG_FS_DIEPCTLx) (x = 1..3, OTG_FS_DIEPCTLx where x = Endpoint_number) on page 739 0xAE0 OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) OTG_FS_DIEPINTx 0x908 (x = 0..3, where x = Endpoint_number) on page 745...
Page 700: Otg_Fs Global Registers
USB on-the-go full-speed (OTG_FS) RM0034 Table 172. Data FIFO (DFIFO) access register map FIFO access register section Address range Access Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access 0x1000–0x1FFC Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access 0x2000–0x2FFC Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access...
Page 701 RM0034 USB on-the-go full-speed (OTG_FS) Bit 19 BSVLD: B-session valid Indicates the Device mode transceiver status. 0: B-session is not valid. 1: B-session is valid. In OTG mode, you can use this bit to determine if the device is connected or disconnected. Note: Only accessible in Device mode.
Page 702 USB on-the-go full-speed (OTG_FS) RM0034 Bit 8 HNGSCS: Host negotiation success The core sets this bit when host negotiation is successful. The core clears this bit when the HNP Request (HNPRQ) bit in this register is set. 0: Host negotiation failure 1: Host negotiation success Note: Only accessible in Device mode.
Page 703 RM0034 USB on-the-go full-speed (OTG_FS) Bit 18 ADTOCHG: A-device timeout change The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect. Note: Accessible in both Device and Host modes. Bit 17 HNGDET: Host negotiation detected The core sets this bit when it detects a host negotiation request on the USB.
Page 704 USB on-the-go full-speed (OTG_FS) RM0034 Bit 8 PTXFELVL: Periodic TxFIFO empty level Indicates when the periodic TxFIFO empty interrupt bit in the Core interrupt register (PTXFE bit in OTG_FS_GINTSTS) is triggered. 0: PTXFE (in OTG_FS_GINTSTS) interrupt indicates that the Periodic TxFIFO is half empty 1: PTXFE (in OTG_FS_GINTSTS) interrupt indicates that the Periodic TxFIFO is completely empty Note: Only accessible in Host mode.
Page 705 RM0034 USB on-the-go full-speed (OTG_FS) Bit 30 FDMOD: Force device mode Writing a 1 to this bit forces the core to device mode irrespective of the OTG_FS_ID input pin. 0: Normal mode 1: Force device mode After setting the force bit, the application must wait at least 25 ms before the change takes effect.
Page 706 USB on-the-go full-speed (OTG_FS) RM0034 Bits [2:0] TOCAL: FS timeout calibration The number of PHY clocks that the application programs in this field is added to the full-speed interpacket timeout duration in the core to account for any additional delays introduced by the PHY.
Page 707 RM0034 USB on-the-go full-speed (OTG_FS) Bit 4 RXFFLSH: RxFIFO flush The application can flush the entire RxFIFO using this bit, but must first ensure that the core is not in the middle of a transaction. The application must only write to this bit after checking that the core is neither reading from the RxFIFO nor writing to the RxFIFO.
Page 708 USB on-the-go full-speed (OTG_FS) RM0034 Bit 0 CSRST: Core soft reset Resets the HCLK and PCLK domains as follows: Clears the interrupts and all the CSR register bits except for the following bits: – RSTPDMODL bit in OTG_FS_PCGCCTL – GAYEHCLK bit in OTG_FS_PCGCCTL –...
Page 709 RM0034 USB on-the-go full-speed (OTG_FS) Bit 31 WKUPINT: Resume/remote wakeup detected interrupt In Device mode, this interrupt is asserted when a resume is detected on the USB. In Host mode, this interrupt is asserted when a remote wakeup is detected on the USB. Note: Accessible in both Device and Host modes.
Page 710 USB on-the-go full-speed (OTG_FS) RM0034 Bit 20 IISOIXFR: Incomplete isochronous IN transfer The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register.
Page 711 RM0034 USB on-the-go full-speed (OTG_FS) Bit 7 GONAKEFF: Global OUT NAK effective Indicates that the Set global OUT NAK bit in the Device control register (SGONAK bit in OTG_FS_DCTL), set by the application, has taken effect in the core. This bit can be cleared by writing the Clear global OUT NAK bit in the Device control register (CGONAK bit in OTG_FS_DCTL).
Page 712 USB on-the-go full-speed (OTG_FS) RM0034 OTG_FS interrupt mask register (OTG_FS_GINTMSK) Address offset: 0x018 Reset value: 0x0000 0000 This register works with the Core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the Core Interrupt (OTG_FS_GINTSTS) register bit corresponding to that interrupt is still set.
Page 713 RM0034 USB on-the-go full-speed (OTG_FS) Bit 23 Reserved Bit 22 FSUSPM: Data fetch suspended mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in Device mode. Bit 21 IPXFRM: Incomplete periodic transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in Host mode.
Page 714 USB on-the-go full-speed (OTG_FS) RM0034 Bit 12 USBRST: USB reset mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in Device mode. Bit 11 USBSUSPM: USB suspend mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in Device mode. Bit 10 ESUSPM: Early suspend mask 0: Masked interrupt 1: Unmasked interrupt...
Page 715 RM0034 USB on-the-go full-speed (OTG_FS) OTG_FS Receive status debug read/OTG status read and pop registers (OTG_FS_GRXSTSR/OTG_FS_GRXSTSP) Address offset for Read: 0x01C Address offset for Pop: 0x020 Reset value: 0x0000 0000 A read to the Receive status debug read register returns the contents of the top of the Receive FIFO.
Page 716 USB on-the-go full-speed (OTG_FS) RM0034 Bits 24:21 FRMNUM: Frame number This is the least significant 4 bits of the frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported. Bits 20:17 PKTSTS: Packet status Indicates the status of the received packet 0001: Global OUT NAK (triggers an interrupt)
Page 717 RM0034 USB on-the-go full-speed (OTG_FS) OTG_FS non-periodic transmit FIFO size register (OTG_FS_GNPTXFSIZ) Address offset: 0x028 Reset value: 0x0000 0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 NPTXFD NPTXFSA r/rw...
Page 718 USB on-the-go full-speed (OTG_FS) RM0034 Bits 23:16 NPTQXSAV: Non-periodic transmit request queue space available Indicates the amount of free space available in the non-periodic transmit request queue. This queue holds both IN and OUT requests in Host mode. Device mode has only IN requests.
Page 719 RM0034 USB on-the-go full-speed (OTG_FS) OTG_FS core ID register (OTG_FS_CID) Address offset: 0x03C Reset value:0x00001000 This is a read only register containing the Product ID. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PRODUCT_ID rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 PRODUCT_ID: Product ID field...
Page 720: Host-Mode Registers
USB on-the-go full-speed (OTG_FS) RM0034 Bits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address This field contains the memory start address for IN endpoint transmit FIFOx. 26.6.3 Host-mode registers Bit values in the register descriptions are expressed in binary unless otherwise specified. Host-mode registers affect the operation of the core in the Host mode.
Page 721 RM0034 USB on-the-go full-speed (OTG_FS) OTG_FS Host frame interval register (OTG_FS_HFIR) Address offset: 0x404 Reset value: 0x0000 EA60 This register stores the frame interval information for the current speed to which the OTG_FS controller has enumerated. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FRIVL Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...
Page 722 USB on-the-go full-speed (OTG_FS) RM0034 OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) Address offset: 0x410 Reset value: 0x0008 0100 This read-only register contains the free space information for the periodic TxFIFO and the periodic transmit request queue. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PTXQTOP PTXQSAV PTXFSAVL...
Page 723 RM0034 USB on-the-go full-speed (OTG_FS) OTG_FS Host all channels interrupt register (OTG_FS_HAINT) Address offset: 0x414 Reset value: 0x0000 000 When a significant event occurs on a channel, the Host all channels interrupt register interrupts the application using the Host channels interrupt bit of the Core interrupt register (HCINT bit in OTG_FS_GINTSTS).
Page 724 USB on-the-go full-speed (OTG_FS) RM0034 OTG_FS host port control and status register (OTG_FS_HPRT) Address offset: 0x440 Reset value: 0x0000 0000 This register is available only in Host mode. Currently, the OTG Host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port.
Page 725 RM0034 USB on-the-go full-speed (OTG_FS) Bit 8 PRST: Port reset When the application sets this bit, a reset sequence is started on this port. The application must time the reset period and clear this bit after the reset sequence is complete. 0: Port not in reset 1: Port in reset The application must leave this bit set for a minimum duration of at least 10 ms to start a reset...
Page 726 USB on-the-go full-speed (OTG_FS) RM0034 Bit 1 PCDET: Port connect detected The core sets this bit when a device connection is detected to trigger an interrupt to the application using the Host port interrupt bit in the Core interrupt register (HPRTINT bit in OTG_FS_GINTSTS).
Page 727 RM0034 USB on-the-go full-speed (OTG_FS) Bit 15 EPDIR: Endpoint direction Indicates whether the transaction is IN or OUT. 0: OUT 1: IN Bits 14:11 EPNUM: Endpoint number Indicates the endpoint number on the device serving as the data source or sink. Bits 10:0 MPSIZ: Maximum packet size Indicates the maximum packet size of the associated endpoint.
Page 728 USB on-the-go full-speed (OTG_FS) RM0034 Bit 1 CHH: Channel halted Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. Bit 0 XFRC: Transfer completed Transfer completed normally without any errors. OTG_FS host channel-x interrupt mask register (OTG_FS_HCINTMSKx) (x = 0..7, where x = Channel_number) Address offset: 0x50C + (Channel_number ×...
Page 729 RM0034 USB on-the-go full-speed (OTG_FS) Bit 1 CHHM: Channel halted mask 0: Masked interrupt 1: Unmasked interrupt Bit 0 XFRCM: Transfer completed mask 0: Masked interrupt 1: Unmasked interrupt OTG_FS host channel-x transfer size register (OTG_FS_HCTSIZx) (x = 0..7, where x = Channel_number) Address offset: 0x510 + (Channel_number ×...
Page 730: Device-Mode Registers
USB on-the-go full-speed (OTG_FS) RM0034 26.6.4 Device-mode registers OTG_FS device configuration register (OTG_FS_DCFG) Address offset: 0x800 Reset value: 0x0220 0000 This register configures the core in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw rw rw...
Page 731 RM0034 USB on-the-go full-speed (OTG_FS) OTG_FS device control register (OTG_FS_DCTL) Address offset: 0x804 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw Bits 31:12 Reserved...
Page 732: Table 174. Minimum Duration For Soft Disconnect
USB on-the-go full-speed (OTG_FS) RM0034 Bit 1 SDIS: Soft disconnect The application uses this bit to signal the USB OTG core to perform a soft disconnect. As long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the USB.
Page 733 RM0034 USB on-the-go full-speed (OTG_FS) Bits 2:1 ENUMSPD: Enumerated speed Indicates the speed at which the OTG_FS controller has come up after speed detection through a chirp sequence. 01: Reserved 10: Reserved 11: Full speed (PHY clock is running at 48 MHz) Others: reserved Bit 0 SUSPSTS: Suspend status In Device mode, this bit is set as long as a Suspend condition is detected on the USB.
Page 734 USB on-the-go full-speed (OTG_FS) RM0034 Bit 4 ITTXFEMSK: IN token received when TxFIFO empty mask 0: Masked interrupt 1: Unmasked interrupt Bit 3 TOM: Timeout condition mask (Non-isochronous endpoints) 0: Masked interrupt 1: Unmasked interrupt Bit 2 Reserved Bit 1 EPDM: Endpoint disabled interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bit 0 XFRCM: Transfer completed interrupt mask...
Page 735 RM0034 USB on-the-go full-speed (OTG_FS) Bit 4 OTEPDM: OUT token received when endpoint disabled mask Applies to control OUT endpoints only. 0: Masked interrupt 1: Unmasked interrupt Bit 3 STUPM: SETUP phase done mask Applies to control endpoints only. 0: Masked interrupt 1: Unmasked interrupt Bit 2 Reserved Bit 1 EPDM: Endpoint disabled interrupt mask...
Page 736 USB on-the-go full-speed (OTG_FS) RM0034 OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) Address offset: 0x81C Reset value: 0x0000 0000 The Device endpoint interrupt mask register works with the Device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the Device all endpoints interrupt (OTG_FS_DAINT) register bit corresponding to that interrupt is still set.
Page 737 RM0034 USB on-the-go full-speed (OTG_FS) OTG_FS device V pulsing time register (OTG_FS_DVBUSPULSE) Address offset: 0x082C Reset value: 0x0000 05B8 This register specifies the V pulsing time during SRP. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DVBUSP Reserved rw rw rw rw rw rw rw rw rw rw rw rw...
Page 738 USB on-the-go full-speed (OTG_FS) RM0034 Bit 31 EPENA: Endpoint enable The application sets this bit to start transmitting data on the endpoint 0. The core clears this bit before setting any of the following interrupts on this endpoint: – Endpoint disabled –...
Page 739 RM0034 USB on-the-go full-speed (OTG_FS) Bits 1:0 MPSIZ: Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. 00: 64 bytes 01: 32 bytes 10: 16 bytes 11: 8 bytes OTG device endpoint-x control register (OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number) Address offset: 0x900 + (Endpoint_number ×...
Page 740 USB on-the-go full-speed (OTG_FS) RM0034 Bit 27 SNAK: Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a Transfer completed interrupt, or after a SETUP is received on the endpoint.
Page 741 RM0034 USB on-the-go full-speed (OTG_FS) Bit 16 EONUM: Even/odd frame Applies to isochronous IN endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register.
Page 742 USB on-the-go full-speed (OTG_FS) RM0034 Bits 29:28 Reserved Bit 27 SNAK: Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit on a Transfer completed interrupt, or after a SETUP is received on the endpoint.
Page 743 RM0034 USB on-the-go full-speed (OTG_FS) OTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) (x = 1..3, where x = Endpoint_number) Address offset for OUT endpoints: 0xB00 + (Endpoint_number × 0x20) Reset value: 0x0000 0000 The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
Page 744 USB on-the-go full-speed (OTG_FS) RM0034 Bit 21 STALL: STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority.
Page 745 RM0034 USB on-the-go full-speed (OTG_FS) Bits 14:11 Reserved Bits 10:0 MPSIZ: Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) (x = 0..3, where x = Endpoint_number) Address offset: 0x908 + (Endpoint_number ×...
Page 746 USB on-the-go full-speed (OTG_FS) RM0034 Bit 2 Reserved. Bit 1 EPDISD: Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the application’s request. Bit 0 XFRC: Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
Page 747 RM0034 USB on-the-go full-speed (OTG_FS) Bit 0 XFRC: Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. OTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0) Address offset: 0x910 Reset value: 0x0000 0000 The application must modify this register before enabling endpoint 0.
Page 748 USB on-the-go full-speed (OTG_FS) RM0034 Bit 31 Reserved Bits 30:29 STUPCNT: SETUP packet count This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 01: 1 packet 10: 2 packets 11: 3 packets Bits 28:20 Reserved Bit 19 PKTCNT: Packet count This field is decremented to zero after a packet is written into the RxFIFO.
Page 749 RM0034 USB on-the-go full-speed (OTG_FS) Bits 18:0 XFRSIZ: Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet.
Page 750: Otg_Fs Power And Clock Gating Control Register (Otg_Fs_Pcgcctl)
USB on-the-go full-speed (OTG_FS) RM0034 Bits 30:29 RXDPID: Received data PID Applies to isochronous OUT endpoints only. This is the data PID received in the last packet for this endpoint. 00: DATA0 01: DATA2 10: DATA1 11: MDATA STUPCNT: SETUP packet count Applies to control OUT Endpoints only.
Page 751: Otg_Fs Register Map
RM0034 USB on-the-go full-speed (OTG_FS) Bit 0 STPPCLK: Stop PHY clock The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts.
Page 752 USB on-the-go full-speed (OTG_FS) RM0034 Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_GRXS TSR (Host PKTSTS DPID BCNT CHNUM Reserved mode) Reset value 0x020 OTG_FS_GRXS TSPR (Device FRMNUM PKTSTS DPID BCNT EPNUM Reserved mode) Reset value OTG_FS_GRXF RXFD 0x024...
Page 753 RM0034 USB on-the-go full-speed (OTG_FS) Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_HCC EPNUM MPSIZ HAR0 0x500 Reset value OTG_FS_HCC EPNUM MPSIZ HAR1 0x520 Reset value OTG_FS_HCC EPNUM MPSIZ HAR2 0x540 Reset value OTG_FS_HCC EPNUM MPSIZ HAR3 0x560 Reset value...
Page 754 USB on-the-go full-speed (OTG_FS) RM0034 Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_HCC EPNUM MPSIZ HAR14 0x6C0 Reset value OTG_FS_HCC EPNUM MPSIZ HAR15 0x6E0 Reset value OTG_FS_HCIN 0x508 Reserved Reset value OTG_FS_HCIN 0x528 Reserved Reset value OTG_FS_HCIN 0x548 Reserved...
Page 755 RM0034 USB on-the-go full-speed (OTG_FS) Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_HCIN 0x6C8 Reserved Reset value OTG_FS_HCIN 0x6E8 Reserved Reset value OTG_FS_HCIN TMSK0 0x50C Reserved Reset value OTG_FS_HCIN TMSK1 0x52C Reserved Reset value OTG_FS_HCIN TMSK2 0x54C Reserved Reset value...
Page 756 USB on-the-go full-speed (OTG_FS) RM0034 Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_HCIN TMSK12 0x68C Reserved Reset value OTG_FS_HCIN TMSK13 0x6AC Reserved Reset value OTG_FS_HCIN TMSK14 0x6CC Reserved Reset value OTG_FS_HCIN 0x6EC TMSK15 Reserved Reset value OTG_FS_HCTS DPID PKTCNT...
Page 757 RM0034 USB on-the-go full-speed (OTG_FS) Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_HCTS DPID PKTCNT XFRSIZ IZ13 0x6B0 Reset value OTG_FS_HCTS DPID PKTCNT XFRSIZ IZ14 0x6D0 Reset value OTG_FS_HCTS DPID PKTCNT XFRSIZ IZ15 0x6F0 Reset value OTG_FS_DCFG 0x800 Reserved...
Page 758 USB on-the-go full-speed (OTG_FS) RM0034 Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DIEP TXFNUM MPSIZ CTL1 0x920 Reserved Reset value TG_FS_DTXFS INEPTFSAV 0x938 Reserved Reset value OTG_FS_DIEP TXFNUM MPSIZ CTL2 0x940 Reserved Reset value TG_FS_DTXFS INEPTFSAV 0x958 Reserved Reset value...
Page 759 RM0034 USB on-the-go full-speed (OTG_FS) Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DIEP TXFNUM MPSIZ CTL7 0x9E0 Reserved Reset value OTG_FS_DIEP TXFNUM MPSIZ CTL8 0xA00 Reserved Reset value OTG_FS_DIEP TXFNUM MPSIZ CTL9 0xA20 Reserved Reset value OTG_FS_DIEP TXFNUM MPSIZ...
Page 760 USB on-the-go full-speed (OTG_FS) RM0034 Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DIEP TXFNUM MPSIZ CTL15 0xAE0 Reserved Reset value OTG_FS_DOEP EPTY MPSI CTL0 0xB00 Reserved Reserved Reset value OTG_FS_DOEP MPSIZ 0xB20 CTL1 Reserved Reserved Reset value OTG_FS_DOEP MPSIZ CTL2...
Page 761 RM0034 USB on-the-go full-speed (OTG_FS) Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DOEP MPSIZ CTL7 0xBE0 Reserved Reserved Reset value OTG_FS_DOEP MPSIZ CTL8 0xC00 Reserved Reserved Reset value OTG_FS_DOEP MPSIZ CTL9 0xC20 Reserved Reserved Reset value OTG_FS_DOEP MPSIZ CTL10...
Page 762 USB on-the-go full-speed (OTG_FS) RM0034 Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DOEP MPSIZ CTL15 0xCE0 Reserved Reserved Reset value OTG_FS_DIEPI 0x908 Reserved Reset value OTG_FS_DIEPI 0x928 Reserved Reset value OTG_FS_DIEPI 0x948 Reserved Reset value OTG_FS_DIEPI 0x968 Reserved Reset value...
Page 763 RM0034 USB on-the-go full-speed (OTG_FS) Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DIEPI 0xAA8 NT13 Reserved Reset value OTG_FS_DIEPI NT14 0xAC8 Reserved Reset value OTG_FS_DIEPI NT15 0xAE8 Reserved Reset value OTG_FS_DOEP INT0 0xB08 Reserved Reset value OTG_FS_DOEP INT1 0xB28...
Page 764 USB on-the-go full-speed (OTG_FS) RM0034 Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DOEP INT11 0xC68 Reserved Reset value OTG_FS_DOEP INT12 0xC88 Reserved Reset value OTG_FS_DOEP INT13 0xCA8 Reserved Reset value OTG_FS_DOEP 0xCC8 INT14 Reserved Reset value OTG_FS_DOEP INT15 0xCE8...
Page 765 RM0034 USB on-the-go full-speed (OTG_FS) Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DIEP MCNT PKTCNT XFRSIZ TSIZ12 0xA90 Reset value OTG_FS_DIEP MCNT PKTCNT XFRSIZ TSIZ13 0xAB0 Reset value OTG_FS_DIEP MCNT PKTCNT XFRSIZ TSIZ14 0xAD0 Reset value OTG_FS_DIEP MCNT PKTCNT...
Page 766 USB on-the-go full-speed (OTG_FS) RM0034 Table 175. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DOEP PKTCNT XFRSIZ TSIZ10 0xC50 Reset value OTG_FS_DOEP PKTCNT XFRSIZ TSIZ11 0xC70 Reset value OTG_FS_DOEP PKTCNT XFRSIZ 0xC90 TSIZ12 Reset value OTG_FS_DOEP PKTCNT XFRSIZ TSIZ13 0xCB0 Reset value...
Page 767: Otg_Fs Programming Model
RM0034 OTG_FS programming model OTG_FS programming model 27.1 Core initialization The application must perform the core initialization sequence. If the cable is connected during power-up, the current mode of operation bit in the Core interrupt register (CMOD bit in OTG_FS_GINTSTS) reflects the mode. The OTG_FS controller enters Host mode when an “A”...
Page 768: Device Initialization
OTG_FS programming model RM0034 Program the HPRTINT in GINTMSK to unmask Program the OTG_FS_HCFG register to select full-speed host Program the PPWR bit in OTG_FS_HPRT to 1. This drives V on the USB. Wait for the PCDET interrupt in OTG_FS_HPRT0. This indicates that a device is connecting to the port.
Page 769: Host Programming Model
RM0034 OTG_FS programming model 27.4 Host programming model 27.4.1 Channel initialization The application must initialize one or more channels before it can communicate with connected devices. To initialize and enable a channel, the application must perform the following steps: Program the GINTMSK register to unmask the following: Channel interrupt –...
Page 770: Operational Model
OTG_FS programming model RM0034 and wait for a channel halted interrupt. The application must be able to receive other interrupts (DTERR, Nak, Data, TXERR) for the same channel before receiving the halt. When a DISCINT (Disconnect Device) interrupt in OTG_FS_GINTSTS is received. (The application is expected to disable all enabled channels When the application aborts a transfer before normal completion.
Page 771: Figure 272. Receive Fifo Read Task
RM0034 OTG_FS programming model Figure 272. Receive FIFO read task Start RXFLVL interrupt ? Unmask RXFLVL Mask RXFLVL Unmask RXFLVL interrupt interrupt interrupt Read the received Read packet from the OTG_FS_GRXSTSP Receive FIFO PKTSTS 0b0010? BCNT > 0? ai15674 Bulk and control OUT/SETUP transactions A typical bulk or control OUT/SETUP pipelined transaction-level operation is shown in Figure 273.
Page 772 OTG_FS programming model RM0034 Initialize channel 1 Write the first packet for channel 1 Along with the last DWORD write, the core writes an entry to the non-periodic request queue As soon as the non-periodic queue becomes non-empty, the core attempts to send an OUT token in the current frame Write the second (last) packet for channel 1 The core generates the XFRC interrupt as soon as the last transaction is completed...
Page 773: Figure 273. Normal Bulk/Control Out/Setup And Bulk/Control In Transactions
RM0034 OTG_FS programming model Figure 273. Normal bulk/control OUT/SETUP and bulk/control IN transactions Application Host Device init_reg(ch _1) Non-Periodic Request init _reg(ch_2) Queue write_tx_fifo Assume that this queue (ch_1) can hold 4 entries. set _ch_en (ch _2) ch_1 write_tx_fifo (ch_1) ch_2 set _ch_en ch_1...
Page 774 OTG_FS programming model RM0034 else if (STALL) Transfer Done = 1 Unmask CHH Disable Channel else if (NAK or TXERR ) Rewind Buffer Pointers Unmask CHH Disable Channel if (TXERR) Increment Error Count Unmask ACK else Reset Error Count else if (CHH) Mask CHH if (Transfer Done or (Error_count == 3)) De-allocate Channel...
Page 775 RM0034 OTG_FS programming model else if (TXERR or BBERR or STALL) Unmask CHH Disable Channel if (TXERR) Increment Error Count Unmask ACK else if (CHH) Mask CHH if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel else if (ACK) Reset Error Count Mask ACK else if (DTERR)
Page 776: Figure 274. Bulk/Control In Transactions
OTG_FS programming model RM0034 Figure 274. Bulk/control IN transactions Application Host Device init_reg(ch _1) Non-Periodic Request init _reg(ch_2) Queue write_tx_fifo Assume that this queue (ch_1) can hold 4 entries. set _ch_en (ch _2) ch_1 write_tx_fifo ch_2 (ch_1) set _ch_en ch_1 (ch _2) ch_2 set _ch_en...
Page 777 RM0034 OTG_FS programming model Initialize channel 2. Set the CHENA bit in HCCHAR2 to write an IN request to the non-periodic request queue. The core attempts to send an IN token after completing the current OUT transaction. The core generates an RXFLVL interrupt as soon as the received packet is written to the receive FIFO.
Page 778: Figure 275. Normal Interrupt Out/In Transactions
OTG_FS programming model RM0034 Initialize and enable channel 1. The application must set the ODDFRM bit in OTG_FS_HCCHAR1. Write the first packet for channel 1. For a high-bandwidth interrupt transfer, the application must write the subsequent packets up to MCNT (maximum number of packets to be transmitted in the next frame times) before switching to another channel.
Page 779 RM0034 OTG_FS programming model Interrupt service routine for interrupt OUT/IN transactions Interrupt OUT Unmask (NAK/TXERR/STALL/XFRC/FRMOR) if (XFRC) Reset Error Count Mask ACK De-allocate Channel else if (STALL or FRMOR) Mask ACK Unmask CHH Disable Channel if (STALL) Transfer Done = 1 else if (NAK or TXERR) Rewind Buffer Pointers...
Page 780 OTG_FS programming model RM0034 MCNT field before switching to another channel. The application uses the NPTXFE interrupt in OTG_FS_GINTSTS to find the transmit FIFO space. Interrupt IN Unmask (NAK/TXERR/XFRC/BBERR/STALL/FRMOR/DTERR) if (XFRC) Reset Error Count Mask ACK if (OTG_FS_HCTSIZx.PKTCNT == 0) De-allocate Channel else Transfer Done = 1...
Page 781 RM0034 OTG_FS programming model else Re-initialize Channel (in next b_interval - 1 /Frame) else if (ACK) Reset Error Count Mask ACK The application is expected to write the requests for the same channel when the Request queue space is available up to the count specified in the MCNT field before switching to another channel (if any).
Page 782 OTG_FS programming model RM0034 Isochronous OUT transactions A typical isochronous OUT operation in Slave mode is shown in Figure 276. The assumptions are: The application is attempting to send one packet every frame (up to 1 maximum packet size), starting with an odd frame. (transfer size = 1 024 bytes). The periodic transmit FIFO can hold one packet (1 KB).
Page 783: Figure 276. Normal Isochronous Out/In Transactions
RM0034 OTG_FS programming model Figure 276. Normal isochronous OUT/IN transactions Host Device Application init _reg(ch_1) init_reg(ch _2) Periodic Request Queue Assume that this queue write_tx_fifo can hold 4 entries. (ch_1) set_ch_en ch_1 (ch_2) ch_2 (micro) frame init _reg(ch_1) write_tx_fifo (ch_1) RXFLVL interrupt read_rx_sts read_rx_fifo...
Page 784 OTG_FS programming model RM0034 else if (CHH) Mask CHH De-allocate Channel Code sample: Isochronous IN Unmask (TXERR/XFRC/FRMOR/BBERR) if (XFRC or FRMOR) if (XFRC and (OTG_FS_HCTSIZx.PKTCNT == 0)) Reset Error Count De-allocate Channel else Unmask CHH Disable Channel else if (TXERR or BBERR) Increment Error Count Unmask CHH Disable Channel...
Page 785 RM0034 OTG_FS programming model The sequence of operations is as follows: Initialize channel 2. The application must set the ODDFRM bit in OTG_FS_HCCHAR2. Set the CHENA bit in OTG_FS_HCCHAR2 to write an IN request to the periodic request queue. For a high-bandwidth isochronous transfer, the application must write the OTG_FS_HCCHAR2 register MCNT (maximum number of expected packets in the next frame times) before switching to another channel.
Page 786: Device Programming Model
OTG_FS programming model RM0034 When OTG_FS controller detects a packet babble, it stops writing data into the Rx buffer and waits for the end of packet (EOP). When it detects an EOP, it flushes already written data in the Rx buffer and generates a Babble interrupt to the application. When OTG_FS controller detects a port babble, it flushes the RxFIFO and disables the port.
Page 787: Endpoint Initialization On Setaddress Command
RM0034 OTG_FS programming model 27.5.3 Endpoint initialization on SetAddress command This section describes what the application must do when it receives a SetAddress command in a SETUP packet. Program the OTG_FS_DCFG register with the device address received in the SetAddress command Program the core to send out a status IN packet 27.5.4 Endpoint initialization on SetConfiguration/SetInterface command...
Page 788: Operational Model
OTG_FS programming model RM0034 In the endpoint to be deactivated, clear the USB active endpoint bit in the OTG_FS_DIEPCTLx register (for IN or bidirectional endpoints) or the OTG_FS_DOEPCTLx register (for OUT or bidirectional endpoints). Once the endpoint is deactivated, the core ignores tokens addressed to that endpoint, which results in a timeout on the USB.
Page 789: Figure 277. Receive Fifo Packet Read In Slave Mode
RM0034 OTG_FS programming model These data indicate that an OUT data transfer for the specified OUT endpoint has completed. After this entry is popped from the receive FIFO, the core asserts a Transfer Completed interrupt on the specified OUT endpoint. After the data payload is popped from the receive FIFO, the RXFLVL interrupt (OTG_FS_GINTSTS) must be unmasked.
Page 790 OTG_FS programming model RM0034 determine the correct number of SETUP packets received in the Setup stage of a control transfer. – STUPCNT = 3 in OTG_FS_DOEPTSIZx The application must always allocate some extra space in the Receive data FIFO, to be able to receive up to three SETUP packets on a control endpoint.
Page 791: Figure 278. Processing A Setup Packet
RM0034 OTG_FS programming model Application programming sequence Program the OTG_FS_DOEPTSIZx register. – STUPCNT Wait for the RXFLVL interrupt (OTG_FS_GINTSTS) and empty the data packets from the receive FIFO. Assertion of the STUP interrupt (OTG_FS_DOEPINTx) marks a successful completion of the SETUP Data Transfer. –...
Page 792 OTG_FS programming model RM0034 space availability in the receive FIFO, non-isochronous OUT tokens receive a NAK handshake response, and the core ignores isochronous OUT data packets The core writes the Global OUT NAK pattern to the receive FIFO. The application must reserve enough receive FIFO space to write this data pattern.
Page 793 RM0034 OTG_FS programming model Before disabling any OUT endpoint, the application must enable Global OUT NAK mode in the core. – SGONAK = 1 in OTG_FS_DCTL Wait for the GONAKEFF interrupt (OTG_FS_GINTSTS) Disable the required OUT endpoint by programming the following fields: –...
Page 794 OTG_FS programming model RM0034 (maximum packet size or short packet) written to the receive FIFO decrements the packet count field for that endpoint by 1. – OUT data packets received with bad data CRC are flushed from the receive FIFO automatically.
Page 795 RM0034 OTG_FS programming model Application requirements: All the application requirements for non-isochronous OUT data transfers also apply to isochronous OUT data transfers. For isochronous OUT data transfers, the transfer size and packet count fields must always be set to the number of maximum-packet-size packets that can be received in a single frame and no more.
Page 796 OTG_FS programming model RM0034 Program the OTG_FS_DOEPTSIZx register for the transfer size and the corresponding packet count Program the OTG_FS_DOEPCTLx register with the endpoint characteristics and set the Endpoint Enable, ClearNAK, and Even/Odd frame bits. – EPENA = 1 – CNAK = 1 –...
Page 797 RM0034 OTG_FS programming model endpoints. At this point, the endpoint with the incomplete transfer remains enabled, but no active transfers remain in progress on this endpoint on the USB. Application programming sequence: Asserting the IISOOXFRM interrupt (OTG_FS_GINTSTS) indicates that in the current frame, at least one isochronous OUT endpoint has an incomplete transfer.
Page 798: In Data Transfers
OTG_FS programming model RM0034 Figure 279 depicts the reception of a single Bulk OUT Data packet from the USB to the AHB and describes the events involved in the process. Figure 279. Slave mode bulk OUT transaction Application Host Device init_ out_ ep XFRSIZ = 512 bytes PKTCNT = 1...
Page 799 RM0034 OTG_FS programming model The application can either choose the polling or the interrupt mode. – In polling mode, the application monitors the status of the endpoint transmit data FIFO by reading the G_FS_DTXFSTSx register, to determine if there is enough space in the data FIFO.
Page 800 OTG_FS programming model RM0034 To stop transmitting any data on a particular IN endpoint, the application must set the IN NAK bit. To set this bit, the following field must be programmed. – SNAK = 1 in OTG_FS_DIEPCTLx Wait for assertion of the INEPNE interrupt in OTG_FS_DIEPINTx. This interrupt indicates that the core has stopped transmitting data on the endpoint.
Page 801 RM0034 OTG_FS programming model Generic non-periodic IN data transfers Application requirements: Before setting up an IN transfer, the application must ensure that all data to be transmitted as part of the IN transfer are part of a single buffer. For IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a payload that constitutes multiple maximum-packet-size packets and a single short packet.
Page 802 OTG_FS programming model RM0034 handshake, the packet count for the endpoint is decremented by one, until the packet count is zero. The packet count is not decremented on a timeout. For zero length packets (indicated by an internal zero length flag), the core sends out a zero-length packet for the IN token and decrements the packet count field.
Page 803 RM0034 OTG_FS programming model transmit a few maximum-packet-size packets and a short packet at the end of the transfer, the following conditions must be met: transfer size[EPNUM] = x × MPSIZ[EPNUM] + sp (where x is an integer ≥ 0, and 0 ≤ sp < MPSIZ[EPNUM]) If (sp >...
Page 804 OTG_FS programming model RM0034 – For isochronous endpoints, when a zero- or non-zero-length data packet is transmitted – For interrupt endpoints, when an ACK handshake is transmitted – When the transfer size and packet count are both 0, the transfer completed interrupt for the endpoint is generated and the endpoint enable is cleared.
Page 805 RM0034 OTG_FS programming model The application must stop writing the data payload to the transmit FIFO as soon as possible. The application must set the NAK bit and the disable bit for the endpoint. The core disables the endpoint, clears the disable bit, and asserts the Endpoint Disable interrupt for the endpoint.
Page 806: Worst Case Response Time
OTG_FS programming model RM0034 Special case: stalling the control OUT endpoint The core must stall IN/OUT tokens if, during the data stage of a control transfer, the host sends more IN/OUT tokens than are specified in the SETUP packet. In this case, the application must enable the ITTXFE interrupt in OTG_FS_DIEPINTx and the OTEPDIS interrupt in OTG_FS_DOEPINTx during the data stage of the control transfer, after the core has transferred the amount of data specified in the SETUP packet.
Page 807: Otg Programming Model
RM0034 OTG_FS programming model The application can use the following formula to calculate the value of TRDT: 4 × AHB clock + 1 PHY clock = (2 clock sync + 1 clock memory address + 1 clock memory data from sync RAM) + (1 PHY clock (next PHY clock MAC can sample the 2 clock FIFO outputs) Figure 280.
Page 808: A-Device Session Request Protocol
OTG_FS programming model RM0034 27.8.1 A-device session request protocol The application must set the SRP-capable bit in the Core USB configuration register. This enables the OTG_FS controller to detect SRP as an A-device. Figure 281. A-Device SRP Suspend DRV_VBUS VBUS_VALID pulsing A_VALID Connect...
Page 809: Figure 282. B-Device Srp
RM0034 OTG_FS programming model Figure 282. B-device SRP Suspend VBUS_VALID B_VALID DISCHRG_VBUS SESS_END Data line pulsing Connect pulsing CHRG_VBUS ai15682 1. VBUS_VALID = V valid signal from PHY B_VALID = B-peripheral valid session to PHY DISCHRG_VBUS = discharge signal to PHY SESS_END = session end signal to PHY CHRG_VBUS = charge V signal to PHY...
Page 810: A-Device Host Negotiation Protocol
OTG_FS programming model RM0034 status change bit in the OTG interrupt status register. The application reads the session request success bit in the OTG control and status register. When the USB is powered, the OTG_FS controller connects, completing the SRP process.
Page 811: B-Device Host Negotiation Protocol
RM0034 OTG_FS programming model and status register to indicate to the OTG_FS controller that the B-device supports HNP. When it has finished using the bus, the application suspends by writing the Port suspend bit in the Host port control and status register. When the B-device observes a USB suspend, it disconnects, indicating the initial condition for HNP.
Page 812: Figure 284. B-Device Hnp
OTG_FS programming model RM0034 Figure 284. B-device HNP OTG core Device Host Device Suspend 2 Connect Reset Traffic Traffic D+PULLDOWN D-PULLDOWN ai15684 1. D+PULLDOWN = signal from core to PHY to enable/disable the pull-down on the D+ line inside the PHY. D-PULLDOWN = signal from core to PHY to enable/disable the pull-down on the D- line inside the PHY.
Page 813 RM0034 OTG_FS programming model host negotiation success. The application must read the current Mode bit in the Core interrupt register (OTG_FS_GINTSTS) to determine Host mode operation. The application sets the reset bit (PRST in OTG_FS_HPRT) and the OTG_FS controller issues a USB reset and enumerates the A-device for data traffic. The OTG_FS controller continues the host role of initiating traffic, and when done, suspends the bus by writing the Port suspend bit in the Host port control and status register.
Page 814: Ethernet (Eth): Media Access Control (Mac) With Dma Controller
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 815: Mac Core Features
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller 28.2.1 MAC core features Supports 10/100 Mbit/s data transfer rates with external PHY interfaces IEEE 802.3-compliant MII interface to communicate with an external Fast Ethernet Supports both full-duplex and half-duplex operations –...
Page 816: Dma Features
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Store-and-Forward mode Option to forward under-sized good frames Supports statistics by generating pulses for frames dropped or corrupted (due to overflow) in the Receive FIFO Supports Store and Forward mechanism for transmission to the MAC core Automatic generation of PAUSE frame control or back pressure signal to the MAC core based on Receive FIFO-fill (threshold configurable) level Handles automatic retransmission of Collision frames for transmission...
Page 817: Ethernet Pins And Internal Signals
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller 28.3 Ethernet pins and internal signals Table 176 shows the MAC signals and the corresponding MII/RMII default or remapped signals. It also indicates the pins onto which the signals are input or output, and the pin configuration.
Page 818: Ethernet Functional Description: Smi, Mii And Rmii
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Table 176. Ethernet pin configuration (continued) MAC signals MII default MII remap RMII default RMII remap Pin configuration ETH_MII_RXD2 RXD2 PD11 Floating input (reset state) ETH_MII_RXD3 RXD3 PD12 Floating input (reset state) 28.4 Ethernet functional description: SMI, MII and RMII The Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated...
Page 819: Table 177. Management Frame Format
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller The application can select one of the 32 PHYs and one of the 32 registers within any PHY and send control data or receive status information. Only one register in one PHY can be addressed at any given time Both the MII_MDC clock line and the MII_MDIO data line are implemented as alternate function I/O in the microcontroller:...
Page 820: Figure 287. Mdio Timing And Frame Structure - Write Cycle
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 drive a high-impedance state on the first bit of TA, a zero bit on the second one. For a write transaction, the MAC controller drives a <10> pattern during the TA field. The PHY device must drive a high-impedance state for the 2 bits of TA.
Page 821: Media-Independent Interface: Mii
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Figure 288. MDIO timing and frame structure - Read cycle MDIO 32 1's 0 1 1 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 D15 D14 D1 D0 Start Register address Turn Preamble...
Page 822: Figure 289. Media Independent Interface Signals
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Figure 289. Media independent interface signals TX _CLK STM32 TXD[3:0] TX_ER TX_EN RX_CLK RXD[3:0] External RX_ER RX_DV MDIO ai15622 MII_TX_CLK: continuous clock that provides the timing reference for the TX data transfer.
Page 823: Table 179. Tx Interface Signal Encoding
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller that follows the final nibble. In order to receive the frame correctly, the MII_RX_DV signal must encompass the frame, starting no later than the SFD field. MII_RX_ER: receive error must be asserted for one or more clock periods (MII_RX_CLK) to indicate to the MAC sublayer that an error was detected somewhere in the frame.
Page 824: Reduced Media-Independent Interface: Rmii
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 28.4.3 Reduced media-independent interface: RMII The reduced media-independent interface (RMII) specification reduces the pin count between the STM32F107xx Ethernet peripheral and the external Ethernet in 10/100 Mbit/s. According to the IEEE 802.3u standard, an MII contains 16 pins for data and control. The RMII specification is dedicated to reduce the pin count to 7 pins (a 62.5% decrease in pin count).
Page 825: Mii/Rmii Selection
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Figure 292. RMII clock sources STM32 External 25 MHz REF_CLK For 10/100 Mbit/s 50 MHz 50 MHz ai15625 28.4.4 MII/RMII selection The mode, MII or RMII, is selected using the configuration bit 23, MII_RMII_SEL, in the AFIO_MAPR register.
Page 826: Ethernet Functional Description: Mac 802.3
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 28.5 Ethernet functional description: MAC 802.3 The IEEE 802.3 International Standard for local area networks (LANs) employs the CSMA/CD (carrier sense multiple access with collision detection) as the access method. The Ethernet peripheral consists of a MAC 802.3 (media access control) controller with media independent interface (MII) and a dedicated DMA controller.
Page 827: Figure 294. Address Field Format
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Figure 295 Figure 296 describe the frame structure (untagged and tagged) that includes the following fields: Preamble: 7-byte field used for synchronization purposes (PLS circuitry) Hexadecimal value: 55-55-55-55-55-55-55 Bit pattern: 01010101 01010101 01010101 01010101 01010101 01010101 01010101 (right-to-left bit transmission) Start frame delimiter (SFD): 1-byte field used to indicate the start of a frame.
Page 828 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 hexadecimal). This constant field is used to distinguish tagged and untagged MAC frames. – 2-byte field containing the Tag control information field subdivided as follows: a 3- bit user priority, a canonical format indicator (CFI) bit and a 12-bit VLAN Identifier. The length of the tagged MAC frame is extended by 4 bytes by the QTag Prefix.
Page 829: Figure 295. Mac Frame Format
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Figure 295. MAC frame format 7 bytes Preamble 1 byte 6 bytes Destination address Bytes within frame transmitted 6 bytes Source address top to bottom 2 bytes MAC client length/type MAC client data 46-1500 bytes 4 bytes...
Page 830: Mac Frame Transmission
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 28.5.2 MAC frame transmission The DMA controls all transactions for the transmit path. Ethernet frames read from the system memory are pushed into the FIFO by the DMA. The frame are then popped out and transferred to the MAC core.
Page 831 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller The CRC generator calculates the 32-bit CRC for the FCS field of the Ethernet frame. The encoding is defined by the following polynomial. G x ( ) Transmit protocol The MAC controls the operation of Ethernet frame transmission. It performs the following functions to meet the IEEE 802.3/802.3z specifications.
Page 832 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 4.2.3.2.1 of the IEEE 802.3 specification. The MAC resets its IFG counter if a carrier is detected during the first two-thirds (64-bit times for all IFG values) of the IFG interval. If the carrier is detected during the final one third of the IFG interval, the MAC continues the IFG count and enables the transmitter after the IFG interval.
Page 833 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller status is received from the MAC, it is pushed to the DMA. If the DMA has already completed sending the second packet to the FIFO, the second transmission must wait for the status of the first packet before proceeding to the next frame.
Page 834 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 in the ETH_ETH_DMAOMR register). If the core is configured for Threshold (cut-through) mode, the Transmit checksum offload is bypassed. You must make sure the Transmit FIFO is deep enough to store a complete frame before that frame is transferred to the MAC Core transmitter.
Page 835 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller error, it inserts an IPv4 header checksum if the Ethernet Type field indicates an IPv4 payload. TCP/UDP/ICMP checksum The TCP/UDP/ICMP checksum processes the IPv4 or IPv6 header (including extension headers) and determines whether the encapsulated payload is TCP, UDP or ICMP.
Page 836: Figure 297. Transmission Bit Order
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Figure 297. Transmission bit order Bibit stream MII_TXD[3:0] Nibble stream ai15632 MII/RMII transmit timing diagrams Figure 298. Transmission with no collision MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CS MII_COL ai15631 836/959...
Page 837: Mac Frame Reception
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Figure 299. Transmission with collision MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CS MII_COL ai15651 Figure 300 shows a frame transmission in MII and RMII. Figure 300. Frame transmission in MMI and RMII modes MII_RX_CLK MII_TX_EN MII_TXD[3:0]...
Page 838 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 packet has been transferred. Upon completion of the EOF frame transfer, the status word is popped out and sent to the DMA controller. In Rx FIFO Store-and-forward mode (configured by the RSF bit in the ETH_DMAOMR register), a frame is read out only after being written completely into the Receive FIFO.
Page 839: Table 181. Frame Statuses
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller have enough bytes, as indicated by the IPv4 header’s Length field (or when fewer than 20 bytes are available in an IPv4 or IPv6 header). The receive checksum offload also identifies a TCP, UDP or ICMP payload in the received IP datagrams (IPv4 or IPv6) and calculates the checksum of such payloads properly, as defined in the TCP, UDP or ICMP specifications.
Page 840 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 length, CRC error and Runt Error bits set), indicating the filter fail. In Ethernet power down mode, all received frames are dropped, and are not forwarded to the application. Receive flow control The MAC detects the receiving Pause frame and pauses the frame transmission for the delay specified within the received Pause frame (only in Full-duplex mode).
Page 841: Figure 301. Receive Bit Order
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Receive status word At the end of the Ethernet frame reception, the MAC outputs the receive status to the application (DMA). The detailed description of the receive status is the same as for bits[31:0] in RDES0, given in RDES0: Receive descriptor Word0 on page 875.
Page 842: Mac Interrupts
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Figure 302. Reception with no error MII_RX_CLK MII_RX_DV MII_RXD[3:0] PREAMBLE MII_RX_ERR ai15634 Figure 303. Reception with errors MII_RX_CLK MII_RX_DV MII_RXD[3:0] PREAMBLE MII_RX_ERR ai15635 Figure 304. Reception with false carrier indication MII_RX_CLK MII_RX_DV MII_RXD[3:0]...
Page 843: Mac Filtering
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller The interrupt register bits only indicate the block from which the event is reported. You have to read the corresponding status registers and other registers to clear the interrupt. For example, bit 3 of the Interrupt register, set high, indicates that the Magic packet or Wake-on- LAN frame is received in Power-down mode.
Page 844: Table 182. Destination Address Filtering Table
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 multicast address is compared with the programmed MAC destination address registers (1– 3). Group address filtering is also supported. In Hash filtering mode, the MAC performs imperfect filtering using a 64-bit Hash table. For hash filtering, the MAC uses the 6 upper CRC bits of the received multicast address to index the content of the Hash table.
Page 845: Mac Loopback Mode
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Table 182. Destination address filtering table (continued) Frame DAIF PAM DB DA filter operation type Pass all frames Pass on perfect/group filter match Fail on perfect/Group filter match Pass on hash filter match Unicast Fail on hash filter match Pass on hash or perfect/Group filter...
Page 846: Mac Management Counters: Mmc
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 28.5.7 MAC management counters: MMC The MAC management counters (MMC) maintain a set of registers for gathering statistics on the received and transmitted frames. These include a control register for controlling the behavior of the registers, two 32-bit registers containing generated interrupts (receive and transmit), and two 32-bit registers containing masks for the Interrupt register (receive and transmit).
Page 847: Figure 306. Wakeup Frame Filter Register
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Remote wakeup frame filter register There are eight wakeup frame filter registers. To write on each of them, load the wakeup frame filter register value by value. The wanted values of the wakeup frame filter are loaded by sequentially loading eight times the wakeup frame filter register.
Page 848 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 write to the wakeup frame filter register address. The application enables remote wakeup by writing a 1 to bit 2 in the ETH_MACPMTCSR register. PMT supports four programmable filters that provide different receive frame patterns. If the incoming frame passes the address filtering of Filter Command, and if Filter CRC-16 matches the incoming examined pattern, then the wakeup frame is received.
Page 849: Precision Time Protocol (Ieee1588 Ptp)
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Disable the Transmit DMA (if applicable) and wait for any previous frame transmissions to complete. These transmissions can be detected when Transmit Interrupt (ETH_DMASR register[0]) is received. Disable the MAC transmitter and MAC receiver by clearing the appropriate bits in the MAC configuration register.
Page 850: Figure 307. Networked Time Synchronization
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Figure 307. Networked time synchronization Master clock time Slave clock time Sync message Data at slave clock Follow_up message containing value of t1 Delay_Req message Delay_Resp message containing value of t4 time ai15669 The master broadcasts PTP Sync messages to all its nodes.
Page 851 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller be greater than or equal to the resolution of time stamp counter. The synchronization accuracy target between the master node and the slaves is around 100 ns. The generation, update and modification of the System Time are described in the Section : System Time correction methods.
Page 852: Figure 308. System Time Update Using The Fine Correction Method
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 the reference time between PTP Sync message intervals. In this method, an accumulator sums up the contents of the Addend register as shown in Figure 308. The arithmetic carry that the accumulator generates is used as a pulse to increment the system time counter. The accumulator and the addend are 32-bit registers.
Page 853 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller The algorithm is as follows: At time MasterSyncTime (n) the master sends the slave clock a Sync message. The slave receives this message when its local clock is SlaveClockTime (n) and computes MasterClockTime (n) as: MasterClockTime (n) = MasterSyncTime (n) + MasterToSlaveDelay (n) The master clock count for current Sync cycle, MasterClockCount (n) is given by:...
Page 854: Figure 309. Ptp Trigger Output To Tim2 Itr1 Connection
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Programming steps for system time update in the Coarse correction method To synchronize or update the system time in one process (coarse correction method), perform the following steps: Write the offset (positive or negative) in the Time stamp update high and low registers. Set bit 3 (TSSTU) in the Time stamp control register.
Page 855: Figure 310. Pps Output
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller PTP pulse-per-second output signal This PTP pulse output is used to check the synchronization between all nodes in the network. To be able to test the difference between the local slave clock and the master reference clock, both clocks were given a pulse per second (PPS) output signal that may be connected to an oscilloscope if necessary.
Page 856: Ethernet Functional Description: Dma Controller Operation
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 28.6 Ethernet functional description: DMA controller operation The DMA has independent transmit and receive engines, and a CSR space. The transmit engine transfers data from system memory into the Tx FIFO while the receive engine transfers data from the Rx FIFO into system memory.
Page 857: Initialization Of A Transfer Using Dma
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller 28.6.1 Initialization of a transfer using DMA Initialization for the MAC is as follows: Write to ETH_DMABMR to set STM32F107xx bus access parameters. Write to the ETH_DMAIER register to mask unnecessary interrupt causes. The software driver creates the transmit and receive descriptor lists.
Page 858: Host Data Buffer Alignment
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 28.6.3 Host data buffer alignment The transmit and receive data buffers do not have any restrictions on start address alignment. In our system with 32-bit memory, the start address for the buffers can be aligned to any of the four bytes.
Page 859: Error Response To Dma
(TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet frame data. Once the ST bit (ETH_DMAOMR register[13]) is set, the DMA enters the Run state. While in the Run state, the DMA polls the transmit descriptor list for frames requiring transmission.
Page 860: Figure 312. Txdma Operation In Default Mode
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Figure 312. TxDMA operation in Default mode Start TxDMA Stop TxDMA Start (Re-)fetch next descriptor (AHB) Poll demand error? TxDMA suspended bit set? Transfer data from buffer(s) (AHB) error? Frame xfer complete? Close intermediate Wait for Tx status...
Page 861 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller The DMA operates as described in steps 1–6 of the TxDMA (default mode). Without closing the previous frame’s last descriptor, the DMA fetches the next descriptor. If the DMA owns the acquired descriptor, the DMA decodes the transmit buffer address in this descriptor.
Page 862: Figure 313. Txdma Operation In Osf Mode
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Figure 313. TxDMA operation in OSF mode Start TxDMA Stop TxDMA Start (Re-)fetch next descriptor (AHB) Poll error? demand TxDMA suspended bit set? Previous frame Transfer data from status available buffer(s) (AHB) Time stamp...
Page 863: Figure 314. Transmit Descriptor
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller indicates the last buffer of the frame. After the last buffer of the frame has been transmitted, the DMA writes back the final status information to the transmit descriptor 0 (TDES0) word of the descriptor that has the last segment set in transmit descriptor 0 (TDES0[29]).
Page 864 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 TDES0: Transmit descriptor Word0 The application software has to program the control bits [30:26]+[23:20] plus the OWN bit [31] during descriptor initialization. When the DMA updates the descriptor (or writes it back), it resets all the control bits plus the OWN bit, and reports only the status bits.
Page 865 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Bit 20 TCH: Second address chained When set, this bit indicates that the second address in the descriptor is the next descriptor address rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t care”...
Page 866 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Bit 8 EC: Excessive collision When set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. If the RD (Disable retry) bit in the MAC Configuration register is set, this bit is set after the first collision, and the transmission of the frame is aborted.
Page 867 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller TDES2: Transmit descriptor Word2 TDES2 contains the address pointer to the first buffer of the descriptor. 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TBAP1 Bits 31:0 TBAP1: Transmit buffer 1 address pointer These bits indicate the physical address of Buffer 1.
Page 868: Figure 315. Transmit Descriptor Field Format With Ieee1588 Time Stamp Enabled
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Figure 315. Transmit descriptor field format with IEEE1588 time stamp enabled Ctrl Res. Ctrl Reserved Status [16:0] TDES 0 [30:26] [23:20] [19:18] Reserved Buffer 2 byte count Reserved Buffer 1 byte count TDES 1 [31:29] [28:16]...
Page 869 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Bit 26 DP: Disable pad When set, the MAC does not automatically add padding to a frame shorter than 64 bytes. When this bit is reset, the DMA automatically adds padding and CRC to a frame shorter than 64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit.
Page 870 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Bit 15 ES: Error summary Indicates the logical OR of the following bits: – TDES0[14]: Jabber timeout – TDES0[13]: Frame flush – TDES0[11]: Loss of carrier – TDES0[10]: No carrier –...
Page 871: Rx Dma Configuration
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Bit 2 ED: Excessive deferral When set, this bit indicates that the transmission has ended because of excessive deferral of over 24 288 bit times if the Deferral check (DC) bit in the MAC Control register is set high. Bit 1 UF: Underflow error When set, this bit indicates that the MAC aborted the frame because data arrived late from the RAM memory.
Page 872 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 When the buffer is full or the frame transfer is complete, the Receive engine fetches the next descriptor. If the current frame transfer is complete, the DMA proceeds to step 7. If the DMA does not own the next fetched descriptor and the frame transfer is not complete (EOF is not yet transferred), the DMA sets the Descriptor error bit in RDES0 (unless flushing is disabled).
Page 873: Figure 316. Receive Dma Operation
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Figure 316. Receive DMA operation Start RxDMA Start Stop RxDMA (Re-)Fetch next Poll demand / descriptor new frame available (AHB) RxDMA suspended error? Frame transfer Own bit set? complete? Frame data Flush disabled ? available ? Flush the...
Page 874 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Receive descriptor acquisition The receive engine always attempts to acquire an extra descriptor in anticipation of an incoming frame. Descriptor acquisition is attempted if any of the following conditions is/are satisfied: The receive Start/Stop bit (ETH_DMAOMR register[1]) has been set immediately after the DMA has been placed in the Run state.
Page 875: Figure 317. Rx Dma Descriptor Structure
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Rx DMA descriptors The descriptor structure has been implemented to support buffers of up to 8 KB. This descriptor structure consists of four 32-bit words. These are shown in Figure 317.
Page 876 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Bit 15 ES: Error summary Indicates the logical OR of the following bits: – RDES0[1]: CRC error – RDES0[3]: Receive error – RDES0[4]: Watchdog timeout – RDES0[6]: Late collision – RDES0[7]: Giant frame (This is not applicable when RDES0[7] indicates an IPV4 header checksum error.) –...
Page 877: Table 184. Receive Descriptor 0
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Bit 3 RE: Receive error When set, this bit indicates that the RX_ERR signal is asserted while RX_DV is asserted during frame reception. Bit 2 DE: Dribble bit error When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd nibbles).
Page 878 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 RDES1: Receive descriptor Word1 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RBS2 RBS2 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 DIC: Disable interrupt on completion...
Page 879: Figure 318. Receive Descriptor Fields Format With Ieee1588 Time Stamp Enabled
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller RDES3: Receive descriptor Word3 RDES3 contains the address pointer either to the second data buffer in the descriptor or to the next descriptor. 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RBP2 rw rw rw rw rw rw rw...
Page 880: Dma Interrupts
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 RDES2: Receive descriptor Word2 The table below describes the fields that have different meaning for RDES2 when the receive descriptor is closed and time stamping is enabled. 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RTSL rw rw rw rw rw rw rw...
Page 881: Ethernet Interrupts
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller receive buffer unavailable (ETH_DMASR register[7]) occurs. The driver clears the Receive interrupt. Even then, a new interrupt is generated, due to the active or pending Receive buffer unavailable interrupt. Figure 319. Interrupt scheme MMCI PMTI TBUS...
Page 882: Ethernet Register Descriptions
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 CLK_RX domain, the CPU may spuriously call the interrupt routine a second time even after reading PMT_CSR. Thus, it may be necessary that the firmware polls the Wakeup Frame Received and Magic Packet Received bits and exits the interrupt service routine only when they are found to be at ‘0’.
Page 883 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Bit 16 CSD: Carrier sense disable When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-duplex mode. No error is generated due to Loss of Carrier or No Carrier during such transmission.
Page 884 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Bits 6:5 BL: Back-off limit The Back-off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000 Mbit/s and 512 bit times for 10/100 Mbit/s) the MAC waits before rescheduling a transmission attempt during retries after a collision.
Page 885 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MAC frame filter register (ETH_MACFFR) Address offset: 0x0004 Reset value: 0x0000 0000 The MAC frame filter register contains the filter controls for receiving frames. Some of the controls from this register go to the address check block of the MAC, which performs the first level of address filtering.
Page 886 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Bit 4 PAM: Pass all multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on the HM bit.
Page 887 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MAC hash table low register (ETH_MACHTLR) Address offset: 0x000C Reset value: 0x0000 0000 The Hash table low register contains the lower 32 bits of the multi-cast Hash table. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 HTL: Hash table low This field contains the lower 32 bits of the Hash table.
Page 888 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Bit 0 MB: MII busy This bit should read a logic 0 before writing to ETH_MACMIIAR and ETH_MACMIIDR. This bit must also be reset to 0 during a Write to ETH_MACMIIAR. During a PHY register access, this bit is set to 0b1 by the application to indicate that a read or write access is in progress.
Page 889 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Bits 15:8 Reserved Bit 7 ZQPD: Zero-quanta pause disable When set, this bit disables the automatic generation of Zero-quanta pause control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-quanta pause control frame generation is enabled.
Page 890 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Ethernet MAC VLAN tag register (ETH_MACVLANTR) Address offset: 0x001C Reset value: 0x0000 0000 The VLAN tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames. The MAC compares the 13 and 14 bytes of the receiving frame (Length/Type) with 0x8100, and the following 2 bytes are compared with the VLAN tag;...
Page 891: Figure 320. Ethernet Mac Remote Wakeup Frame Filter Register (Eth_Macrwuffr)
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Figure 320. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR) Filter 0 Byte Mask Wakeup frame filter reg0 Filter 1 Byte Mask Wakeup frame filter reg1 Filter 2 Byte Mask Wakeup frame filter reg2 Filter 3 Byte Mask Wakeup frame filter reg3...
Page 892 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Bit 1 MPE: Magic Packet enable When set, this bit enables the generation of a power management event due to Magic Packet reception. Bit 0 PD: Power down When this bit is set, all received frames will be dropped. This bit is cleared automatically when a magic packet or wakeup frame is received, and Power-down mode is disabled.
Page 893 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MAC interrupt mask register (ETH_MACIMR) Address offset: 0x003C Reset value: 0x0000 0000 The ETH_MACIMR register bits make it possible to mask the interrupt signal due to the corresponding event in the ETH_MACSR register. TSTIM PMTIM Reserved...
Page 894 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Ethernet MAC address 0 low register (ETH_MACA0LR) Address offset: 0x0044 Reset value: 0xFFFF FFFF The MAC address 0 low register holds the lower 32 bits of the 6-byte first MAC address of the station.
Page 895 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MAC address1 low register (ETH_MACA1LR) Address offset: 0x004C Reset value: 0xFFFF FFFF The MAC address 1 low register holds the lower 32 bits of the 6-byte second MAC address of the station.
Page 896 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Ethernet MAC address 2 low register (ETH_MACA2LR) Address offset: 0x0054 Reset value: 0xFFFF FFFF The MAC address 2 low register holds the lower 32 bits of the 6-byte second MAC address of the station.
Page 897: Mmc Register Description
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MAC address 3 low register (ETH_MACA3LR) Address offset: 0x005C Reset value: 0xFFFF FFFF The MAC address 3 low register holds the lower 32 bits of the 6-byte second MAC address of the station.
Page 898 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Ethernet MMC receive interrupt register (ETH_MMCRIR) Address offset: 0x0104 Reset value: 0x0000 0000 The Ethernet MMC receive interrupt register maintains the interrupts generated when receive statistic counters reach half their maximum values. (MSB of the counter is set.) It is a 32-bit wide register.
Page 899 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Bit 21 TGFS: Transmitted good frames status This bit is set when the transmitted, good frames, counter reaches half the maximum value. Bits 20:16 Reserved Bit 15 TGFMSCS: Transmitted good frames more single collision status This bit is set when the transmitted, good frames after more than a single collision, counter reaches half the maximum value.
Page 900 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR) Address offset: 0x0110 Reset value: 0x0000 0000 The Ethernet MMC transmit interrupt mask register maintains the masks for interrupts generated when the transmit statistic counters reach half their maximum value. (MSB of the counter is set).
Page 901 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MMC transmitted good frames after more than a single collision counter register (ETH_MMCTGFMSCCR) Address offset: 0x0150 Reset value: 0x0000 0000 This register contains the number of successfully transmitted frames after more than a single collision in Half-duplex mode.
Page 902: Ieee 1588 Time Stamp Registers
Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Ethernet MMC received frames with alignment error counter register (ETH_MMCRFAECR) Address offset: 0x0198 Reset value: 0x0000 0000 This register contains the number of frames received with alignment (dribble) error. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RFAEC Bits 31:0 RFAEC: Received frames alignment error counter Received frames with alignment error counter...
Page 903 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Bit 5 TSARU: Time stamp addend register update When this bit is set, the Time stamp addend register’s contents are updated to the PTP block for fine correction. This bit is cleared when the update is completed. This register bit must be read as zero before you can set it.
Page 904 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Ethernet PTP time stamp high register (ETH_PTPTSHR) Address offset: 0x0708 Reset value: 0x0000 0000 This register contains the most significant (higher) 32 time bits. This read-only register contains the seconds system time value. The Time stamp high register, along with Time stamp low register, indicates the current value of the system time maintained by the MAC.
Page 905 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet PTP time stamp high update register (ETH_PTPTSHUR) Address offset: 0x0710 Reset value: 0x0000 0000 This register contains the most significant (higher) 32 bits of the time to be written to, added to, or subtracted from the System Time value.
Page 906 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Ethernet PTP time stamp addend register (ETH_PTPTSAR) Address offset: 0x0718 Reset value: 0x0000 0000 This register is used by the software to readjust the clock frequency linearly to match the master clock frequency.
Page 907: Dma Register Description
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet PTP target time low register (ETH_PTPTTLR) Address offset: 0x0720 Reset value: 0x0000 0000 This register contains the lower 32 bits of time to be compared with the system time for interrupt event generation.
Page 908 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Bits 22:17 RDP: Rx DMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This is the maximum value that is used in a single block read/write operation. The RxDMA always attempts to burst as specified in RDP each time it starts a burst transfer on the host bus.
Page 909 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet DMA transmit poll demand register (ETH_DMATPDR) Address offset: 0x1004 Reset value: 0x0000 0000 This register is used by the application to instruct the DMA to poll the transmit descriptor list. The transmit poll demand register enables the Transmit DMA to check whether or not the current descriptor is owned by DMA.
Page 910 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Ethernet DMA receive descriptor list address register (ETH_DMARDLAR) Address offset: 0x100C Reset value: 0x0000 0000 The Receive descriptor list address register points to the start of the receive descriptor list. The descriptor lists reside in the STM32F107xx's physical memory space and must be word-aligned.
Page 911 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet DMA status register (ETH_DMASR) Address offset: 0x1014 Reset value: 0x0000 0000 The Status register contains all the status bits that the DMA reports to the application. The ETH_DMASR register is usually read by the software driver during an interrupt service routine or polling.
Page 912 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Bits 22:20 TPS: Transmit process state These bits indicate the Transmit DMA FSM state. This field does not generate an interrupt. 000: Stopped; Reset or Stop Transmit Command issued 001: Running; Fetching transmit transfer descriptor 010: Running;...
Page 913 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Bit 13 FBES: Fatal bus error status This bit indicates that a bus error occurred, as detailed in [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses. Bits 12:11 Reserved Bit 10 ETS: Early transmit status This bit indicates that the frame to be transmitted was fully transferred to the Transmit FIFO.
Page 914 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Ethernet DMA operation mode register (ETH_DMAOMR) Address offset: 0x1018 Reset value: 0x0000 0000 The operation mode register establishes the Transmit and Receive operating modes and commands. The ETH_DMAOMR register should be the last CSR to be written as part of DMA initialization.
Page 915 110: 24 111: 16 Bit 13 ST: Start/stop transmission When this bit is set, transmission is placed in the Running state, and the DMA checks the transmit list at the current position for a frame to be transmitted. Descriptor acquisition is...
Page 916 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Bits 4:3 RTC: Receive threshold control These two bits control the threshold level of the Receive FIFO. Transfer (request) to DMA starts when the frame size within the Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically.
Page 917 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Bit 16 NISE: Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is cleared, a normal interrupt is disabled. This bit enables the following bits: –...
Page 918 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Bit 6 RIE: Receive interrupt enable When this bit is set with the normal interrupt summary enable bit (ETH_DMAIER register[16]), the receive interrupt is enabled. When this bit is cleared, the receive interrupt is disabled. Bit 5 TUIE: Underflow interrupt enable When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register[15]), the transmit underflow interrupt is enabled.
Page 919 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet DMA missed frame and buffer overflow counter register (ETH_DMAMFBOCR) Address offset: 0x1020 Reset value: 0x0000 0000 The DMA maintains two counters to track the number of missed frames during reception. This register reports the current value of the counter.
Page 920 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Ethernet DMA current host receive descriptor register (ETH_DMACHRDR) Address offset: 0x104C Reset value: 0x0000 0000 The Current host receive descriptor register points to the start address of the current receive descriptor read by the DMA.
Page 921: Ethernet Register Maps
RM0034 Ethernet (ETH): media access control (MAC) with DMA controller 28.8.5 Ethernet register maps Table 185 gives the ETH register map and reset values. Table 185. Ethernet register map and reset values Offset Register ETH_MACCR 0x00 Reserved Reset value ETH_MACFF 0x04 Reserved Reset value...
Page 922 Ethernet (ETH): media access control (MAC) with DMA controller RM0034 Table 185. Ethernet register map and reset values (continued) Offset Register ETH_MACA3 AE SA MACA3H 0x58 Reserved Reset value ETH_MACA3 MACA3L 0x5C Reset value ETH_MMCCR 0x100 Reserved Reset value ETH_MMCRI 0x104 Reserved Reserved...
Page 923 RM0034 Ethernet (ETH): media access control (MAC) with DMA controller Table 185. Ethernet register map and reset values (continued) Offset Register ETH_PTPTS 0x718 Reset value ETH_PTPTT TTSH 0x71C Reset value ETH_PTPTTL TTSL 0x720 Reset value ETH_DMABM RTPR 0x1000 Reserved Reset value ETH_DMATP 0x1004 Reset value...
Page 924: Device Electronic Signature
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 925: Unique Device Id Register (96 Bits)
RM0034 Device electronic signature 29.2 Unique device ID register (96 bits) The unique device identifier is ideally suited: for use as serial numbers (for example USB string serial numbers or other end applications) for use as security keys in order to increase the security of code in Flash memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal Flash memory to activate secure boot processes, etc.
Page 926 Device electronic signature RM0034 Address offset: 0x08 Read only = 0xXXXX XXXX where X is factory-programmed U_ID(95:80) U_ID(79:64) Bits 31:0 U_ID(95:64): 95:64 Unique ID bits. 926/959...
Page 927: Debug Support (Dbg)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Page 928: Figure 321. Block Diagram Of Stm32F10Xxx-Level And Cortex-M3-Level Debug Support
Bus Matrix DCode interface Data Cortex-M3 System Core interface JTMS/ SWDIO External Private TRACESWO Peripheral Bus (PPB) JTDI Trace Port TRACECK Bridge TPIU JTDO/ SWJ-DP AHB-AP TRACESWO TRACED[3:0] JNTRST Internal Private NVIC Peripheral Bus (PPB) JTCK/ SWCLK DBGMCU The ARM Cortex-M3 core provides integrated on-chip debug support. It is comprised of: SWJ-DP: Serial wire / JTAG debug port AHP-AP: AHB access ITM: Instrumentation trace macrocell...
Page 929: Reference Arm Documentation
Cortex™-M3 r1p1 Technical Reference Manual (TRM) ARM Debug Interface V5 ARM CoreSight Design Kit revision r1p0 Technical Reference Manual SWJ debug port (serial wire and JTAG) The STM32F10xxx core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an ARM standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW- DP (2-pin) interface.
Page 930: Pinout And Debug Port Pins
Debug support (DBG) RM0034 JTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only the SWCLK and SWDIO pins. This sequence is: Send more than 50 TCK cycles with TMS (SWDIO) =1 Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted first) Send more than 50 TCK cycles with TMS (SWDIO) =1 30.4...
Page 931: Internal Pull-Up And Pull-Down On Jtag Pins
RM0034 Debug support (DBG) Three control bits allow the configuration of the SWJ-DP pin assignments. These bits are reset by the System Reset. REMAP_AF_REG (@ 0x4001 0004 in STM32F10xxx MCU) – READ: APB - No Wait State – WRITE: APB - 1 Wait State if the write buffer of the AHB-APB bridge is full. Bit 26:24= SWJ_CFG[2:0] Set and cleared by software.
Page 932: Using Serial Wire And Releasing The Unused Debug Pins As Gpios
Debug support (DBG) RM0034 Once a JTAG I/O is released by the user software, the GPIO controller takes control again. The reset states of the GPIO control registers put the I/Os in the equivalent state: JNTRST: Input pull-up JTDI: Input pull-up JTMS/SWDIO: Input pull-up JTCK/SWCLK: Input pull-down JTDO: Input floating...
Page 933: Id Codes And Locking Mechanism
30.6.1 MCU device ID code The STM32F10xxx MCU integrates an MCU ID code. This ID identifies the ST MCU part- number and the die revision. It is part of the DBG_MCU component and is mapped on the external PPB bus (see Section 30.15 on page...
Page 934: Boundary Scan Tap
Debug support (DBG) RM0034 Bits 31:16 REV_ID(15:0) Revision identifier This field indicates the revision of the device: In low-density devices: – 0x1000 = Revision A In medium-density devices: – 0x0000 = Revision A – 0x2000 = Revision B – 0x2001 = Revision Z –...
Page 935: Cortex-M3 Jedec-106 Id Code
RM0034 Debug support (DBG) 30.6.4 Cortex-M3 JEDEC-106 ID code The ARM Cortex-M3 integrates a JEDEC-106 ID code. It is located in the 4KB ROM table mapped on the internal PPB bus at address 0xE00FF000_0xE00FFFFF. This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two pins) or by the user software.
Page 936: Table 189. 32-Bit Debug Port Registers Addressed Through The Shifted Value A[3:2]
Debug support (DBG) RM0034 Table 188. JTAG debug port data registers IR(3:0) Data register Details Access Port Access Register Initiates an access port and allows access to an access port register. – When transferring data IN: Bits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request Bits 2:1 = A[3:2] = 2-bit address (sub-address AP registers).
Page 937: Sw Debug Port
RM0034 Debug support (DBG) 30.8 SW debug port 30.8.1 SW protocol introduction This synchronous serial protocol uses two pins: SWCLK: clock from host to target SWDIO: bidirectional The protocol allows two banks of registers (DPACC registers and APACC registers) to be read and written to.
Page 938: Sw-Dp State Machine (Reset, Idle States, Id Code)
Debug support (DBG) RM0034 Table 191. ACK response (3 bits) Name Description 001: FAULT 0..2 010: WAIT 100: OK The ACK Response must be followed by a turnaround time only if it is a READ transaction or if a WAIT or FAULT acknowledge has been received. Table 192.
Page 939: Sw-Dp Registers
Access to these registers are initiated when APnDP=0 Table 193. SW-DP registers CTRLSEL bit A(3:2) of SELECT Register Notes register The manufacturer code is not set to ST Read IDCODE code. 0x1BA01477 (identifies the SW-DP) Write ABORT Purpose is to: – request a system or debug power-up –...
Page 940: Ahb-Ap (Ahb Access Port) - Valid For Both Jtag-Dp Or Sw-Dp
Debug support (DBG) RM0034 There are many AP Registers (see AHB-AP) addressed as the combination of: The shifted value A[3:2] The current value of the DP SELECT register 30.9 AHB-AP (AHB Access Port) - valid for both JTAG-DP or SW- Features: System access is independent of the processor status.
Page 941: Capability Of The Debugger Host To Connect Under System Reset
RM0034 Debug support (DBG) It consists of 4 registers: Table 195. Core debug registers Register Description The 32-bit Debug Halting Control and Status Register DHCSR This provides status information about the state of the processor enable core debug halt and step the processor The 17-bit Debug Core Register Selector Register: DCRSR This selects the processor register to transfer data to or from.
Page 942: Fpb (Flash Patch Breakpoint)
Debug support (DBG) RM0034 30.12 FPB (Flash patch breakpoint) The FPB unit: implements hardware breakpoints patches code and data from code space to system space. This feature gives the possibility to correct software bugs located in the Code Memory Space. The use of a Software Patch or a Hardware Breakpoint is exclusive.
Page 943: Timestamp Packets, Synchronization And Overflow Packets
RM0034 Debug support (DBG) The packets emitted by the ITM are output to the TPIU (Trace Port Interface Unit). The formatter of the TPIU adds some extra packets (refer to TPIU) and then output the complete packets sequence to the debugger host. The bit TRCEN of the Debug Exception and Monitor Control Register must be enabled before you program or use the ITM.
Page 944: Mcu Debug Component (Mcudbg)
Debug support (DBG) RM0034 Table 196. Main ITM registers Address Register Details Bit 3: mask to enable tracing ports31:24 Bit 2: mask to enable tracing ports23:16 @E0000E40 ITM Trace Privilege Bit 1: mask to enable tracing ports15:8 Bit 0: mask to enable tracing ports7:0 Each bit enables the corresponding Stimulus port to generate @E0000E00 ITM Trace Enable...
Page 945: Debug Support For Timers, Watchdog, Bxcan And I
RM0034 Debug support (DBG) For this, the debugger host must first set some debug configuration registers to change the low-power mode behavior: In Sleep mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by the debugger. This will feed HCLK with the same clock that is provided to FCLK (system clock previously configured by the software).
Page 946 Debug support (DBG) RM0034 Bits 31:22 Reserved, must be kept cleared. Bit 21 DBG_CAN2_STOP: Debug CAN2 stopped when core is halted 0: Same behavior as in normal mode. 1: CAN2 receive registers are frozen. Bits 20:17 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=8..5) 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
Page 947: Tpiu (Trace Port Interface Unit)
RM0034 Debug support (DBG) Bit 2 DBG_STANDBY: Debug Standby mode 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. From software point of view, exiting from Standby is identical than fetching reset vector (except a few status bit indicated that the MCU is resuming from Standby) 1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active.
Page 948: Trace Pin Assignment
Debug support (DBG) RM0034 Figure 324. TPIU block diagram TRACECLKIN Domain CLK Domain TPIU TRACECLKIN TRACECK Asynchronous Trace Out TPIU TRACEDATA Formatter FIFO (serializer) [3:0] TRACESWO External PPB Bus 30.16.2 TRACE pin assignment Asynchronous mode The asynchronous mode requires 1 extra pin and is available on all packages. It is only available if using Serial Wire mode (not in JTAG mode).
Page 949: Table 199. Flexible Trace Pin Assignment
RM0034 Debug support (DBG) TPUI TRACE pin assignment By default, these pins are NOT assigned. They can be assigned by setting the IOTRACEN and IOTRACEMODE bits of the MCU Debug Component Configuration Register. This configuration has to be done by the debugger host. In addition, the number of pins to assign depends on the trace configuration (asynchronous or synchronous).
Page 950: Tpui Formatter
Debug support (DBG) RM0034 The debugger must then program the Trace Mode by writing the PROTOCOL[1:0] bits in the SPP_R (Selected Pin Protocol) register of the TPIU. PROTOCOL=00: Trace Port Mode (synchronous) PROTOCOL=01 or 10: Serial Wire (Manchester or NRZ) Mode (asynchronous mode). Default state is 01 It then also configures the TRACE port size by writing the bits [3:0] in the CPSPS_R (Current Sync Port Size Register) of the TPIU:...
Page 951: Tpui Frame Synchronization Packets
RM0034 Debug support (DBG) 30.16.4 TPUI frame synchronization packets The TPUI can generate two types of synchronization packets: The Frame Synchronization packet (or Full Word Synchronization packet) It consists of the word: 0x7F_FF_FF_FF (LSB emitted first). This sequence can not occur at any other time provided that the ID source code 0x7F has not been used.
Page 952: Asynchronous Mode
Debug support (DBG) RM0034 30.16.7 Asynchronous mode This is a low cost alternative to output the trace using only 1 pin: this is the asynchronous output pin TRACESWO. Obviously there is a limited bandwidth. TRACESWO is multiplexed with JTDO when using the SW-DP pin. This way, this functionality is available in all STM32F10xxx packages.
Page 953: 30.16.10 Example Of Configuration
RM0034 Debug support (DBG) Table 200. Important TPIU registers (continued) Address Register Description Bit 31-9 = always ‘0’ Bit 8 = TrigIn = always ‘1’ to indicate that triggers are indicated Bit 7-4 = always 0 Bit 3-2 = always 0 Bit 1 = EnFCont.
Page 954: Dbg Register Map
Debug support (DBG) RM0034 30.17 DBG register map The following table summarizes the Debug registers. Table 201. DBG register map and reset values Addr. Register DBGMCU_ REV_ID DEV_ID IDCODE Reserved Reset value DBGMCU_CR Reserved Reset value 1. The reset value is product dependent. For more information, refer to Section 30.6.1: MCU device ID code.
Page 955: Revision History
RM0034 Revision history Revision history Table 202. Document revision history Date Revision Changes 26-Mar-2009 Initial release. 955/959...
Page 956 RM0034 Index Index CAN_TDHxR ......568 CAN_TDLxR ......568 ADC_CR1 .
Page 957 RM0034 Index ETH_MACMIIDR ..... .888 IWDG_KR ......394 ETH_MACPMTCSR .
Page 958 Index RM0034 OTG_FS_HPTXFSIZ ....719 SPI_RXCRCR ......612 OTG_FS_HPTXSTS .
Page 959 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

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