Debug Mode; Figure 140. Triggering Timer 1 And 2 With Timer 1 Ti1 Input - ST STM32F102 Series Reference Manual

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When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on

the internal clock and both TIF flags are set.

In this example both timers are initialized before starting (by setting their respective UG

bits). Both counters starts from 0, but you can easily insert an offset between them by

writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode

insert a delay between CNT_EN and CK_PSC on timer 1.

TIMER1-CEN=CNT_EN

TIMER 1-CK_PSC

TIMER2-CEN=CNT_EN

TIMER 2-CK_PSC

Debug mode

When the microcontroller enters debug mode (Cortex-M3 core - halted), the TIMx counter

either continues to work normally or stops, depending on DBG_TIMx_STOP configuration

bit in DBG module. For more details, refer to

watchdog, bxCAN and

02 03 04 05 06 07 08 09

Section 26.15.2: Debug support for timers,

General-purpose timer (TIMx)

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