RM0008
Figure 162. ModeA write accesses
The differences compared with mode1 are the toggling of NOE and the independent read
and write timings.
Table 77.
Bit
number
31-16
15
14
13-10
9
8
7
6
5-4
3-2
1
0
A[25:0]
NBL[1:0]
NEx
NOE
NWE
D[15:0]
FSMC_BCRx bit fields
Bit name
0x0000
0x0
EXTMOD
0x1
0x0
WAITPOL
Meaningful only if bit 15 is 1.
BURSTEN
0x0
-
FACCEN
-
MWID
As needed
MTYP
As needed, exclude 10 (NOR Flash).
MUXEN
0x0
MBKEN
0x1
Flexible static memory controller (FSMC)
Memory transaction
(ADDSET +1)
HCLK cycles
Value to set
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
ai14721b
377/690
Need help?
Do you have a question about the STM32F102 Series and is the answer not in the manual?