Control Register 3 (Usart_Cr3) - ST STM32F102 Series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
24.6.6

Control register 3 (USART_CR3)

Address offset: 0x14
Reset value: 0x0000
31 30 29
15 14 13
Reserved
Res.
Bits 31:11 Reserved, forced by hardware to 0.
Bit 10 CTSIE: CTS Interrupt Enable.
0: Interrupt is inhibited
1: An interrupt is generated whenever CTS=1 in the USART_SR register
Note: This bit is not available for UART4 & UART5.
Bit 9 CTSE: CTS Enable.
0: CTS hardware flow control disabled
1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the
nCTS input is deasserted while a data is being transmitted, then the transmission is completed
before stopping. If a data is written into the data register while nCTS is asserted, the transmission is
postponed until nCTS is asserted.
Note: This bit is not available for UART4 & UART5.
Bit 8 RTSE: RTS Enable.
0: RTS hardware flow control disabled
1: RTS interrupt enabled, data is only requested when there is space in the receive buffer. The
transmission of data is expected to cease after the current character has been transmitted. The
nRTS output is asserted (tied to 0) when a data can be received.
Note: This bit is not available for UART4 & UART5.
Bit 7 DMAT: DMA Enable Transmitter.
This bit is set/reset by software
1: DMA mode is enabled for transmission.
0: DMA mode is disabled for transmission.
Note: This bit is not available for UART5.
Bit 6 DMAR: DMA Enable Receiver.
This bit is set/reset by software
1: DMA mode is enabled for reception.
0: DMA mode is disabled for reception.
Note: This bit is not available for UART5.
Bit 5 SCEN: Smartcard mode enable.
This bit is used for enabling Smartcard mode.
0: Smartcard Mode disabled
1: Smartcard Mode enabled
Note: This bit is not available for UART4 & UART5.
646/690
28 27 26 25
12 11 10 9
CTSIE CTSE
rw rw
24 23 22 21
Reserved
8 7 6 5
RTSE DMAT DMAR SCEN
rw rw rw rw
20 19 18 17
4 3 2 1
HD
NACK IRLP IREN
SEL
rw rw rw rw
RM0008
16
0
EIE
rw