ST STM32F102 Series Reference Manual page 408

Flexible static memory controller (FSMC)
Common memory space timing register 2..4 (FSMC_PMEM2..4)
Address offset: Address: 0xA000 0000 + 0x48 + 0x20 * (x – 1), x = 2..4
Reset value: 0xFCFC FCFC
Each FSMC_PMEMx (x = 2..4) read/write register contains the timing information for PC
Card or NAND Flash memory bank x, used for access to the common memory space of the
16-bit PC Card/CompactFlash, or to access the NAND Flash for command, address write
access and data read/write access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MEMHIZx
r/w
Bits 31:24 MEMHIZx: Common memory x data bus HiZ time.
Defines the number of HCLK (+1 only for NAND) clock cycles during which the databus is kept in
HiZ after the start of a PC-CARD/NAND Flash write access to common memory space on socket x.
Only valid for write transaction:
0000 0000: (0x00) 0 HCLK cycle
1111 1111: (0xFF) 255 HCLK cycles (default value after reset)
Bits 23:16 MEMHOLDx: Common memory x hold time.
Defines the number of HCLK clock cycles to hold address (and data for write access) after the
command deassertion (NWE, NOE), for PC-CARD/NAND Flash read or write access to common
memory space on socket x:
0000 0000: reserved, do not use this value
0000 0001: 1 HCLK cycle to 255 HCLK cycles (default value after reset)
1111 1111: (0xFF)
Bits 15:8 MEMWAITx: Common memory x wait time.
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for
PC-CARD/NAND Flash read or write access to common memory space on socket x. The duration
for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the
programmed value of HCLK:
0000 0000: 1 HCLK cycle (+ wait cycle introduced by deassertion of NWAIT)
1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default
value after reset)
Bits 7:0 MEMSETx: Common memory x setup time.
Defines the number of HCLK (+1 for PC Card, +2 for NAND) clock cycles to set up the address
before the command assertion (NWE, NOE), for PC CARD/NAND Flash read or write access to
common memory space on socket x:
0000 0000: 1 HCLK cycle
1111 1111: 256 HCLK cycles (default value after reset)
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MEMHOLDx
r/w
9 8 7
MEMWAITx
r/w
RM0008
6 5 4 3 2 1 0
MEMSETx
r/w