ST STM32F102 Series Reference Manual page 37

RM0008
Table 1.
Boundary address
0x4000 7800 - 0x4000 FFFF Reserved
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF Backup registers (BKP)
0x4000 6800 - 0x4000 6BFF Reserved
0x4000 6400 - 0x4000 67FF
0x4000 6000 - 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF USB Registers
0x4000 5800 - 0x4000 5BFF I2C2
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF UART4
0x4000 4800 - 0x4000 4BFF USART3
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 3FFF
0x4000 3C00 - 0x4000 3FFF SPI3/I2S
0x4000 3800 - 0x4000 3BFF SPI2/I2S
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF Window watchdog (WWDG)
0x4000 2800 - 0x4000 2BFF RTC
0x4000 1800 - 0x4000 27FF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF TIM5 timer
Register boundary addresses (continued)
DAC
Power control PWR
bxCAN
Shared USB/CAN SRAM 512
bytes
I2C1
UART5
USART2
Reserved
Reserved
Independent watchdog (IWDG)
Reserved
TIM7 timer
TIM6 timer
Peripheral
APB1
Memory and bus architecture
Bus Register map
Section 11.5.14 on page
205
Section 4.4.3 on page 60
Section 5.4.5 on page 66
Section 21.6.5 on page
537
Section 20.5.4 on page
497
Section 23.6.10 on page
609
Section 23.6.10 on page
609
Section 24.6.8 on page
649
Section 24.6.8 on page
649
Section 24.6.8 on page
649
Section 24.6.8 on page
649
Section 22.5 on page 569
Section 22.5 on page 569
Section 16.4.5 on page
359
Section 17.6.4 on page
364
Section 15.4.7 on page
353
Section 14.4.9 on page
341
Section 14.4.9 on page
341
Section 13.4.19 on page
328
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