Debug Mcu Configuration Register - ST STM32F102 Series Reference Manual

RM0008
For the bxCAN, the user can choose to block the update of the receive register during a
breakpoint.
2
For the I
26.15.3

Debug MCU configuration register

This register allows the configuration of the MCU under DEBUG. This concerns:
●
Low-power mode support
●
Timer and Watchdog counters support
●
bxCAN communication support
●
Trace pin assignment
This DBGMCU_CR is mapped on the External PPB bus at address 0xE004 2004
It is asynchronously reset by the PORESET (and not the system reset). It can be written by
the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.
DBGMCU_CR
Address: 0xE0042004
Only 32-bit access supported
POR Reset: 0x00000000 (not reset by system reset)
31 30 29 28
15 14 13 12
DBG_I
2C1_S DBG_ DBG_ DBG_
MBUS CAN_ TIM4_ TIM3_
_TIME STOP STOP STOP
OUT
rw rw rw rw
Bits 31:21 Reserved, must be kept cleared.
Bits 20:17 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=8..5)
0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave
normally.
1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are
disabled (as if there were an emergency stop in response to a break event).
Bit 16 DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode.
1: The SMBUS timeout is frozen
Bit 15 DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode.
1: The SMBUS timeout is frozen.
C, the user can choose to block the SMBUS timeout during a breakpoint.
27 26 25
Reserved
Res.
11 10 9
DBG_
DBG_ DBG_
WWDG
TIM2_ TIM1_
_
STOP STOP
STOP
rw rw rw
24 23 22 21
8 7 6
DBG_ TRACE_ TRACE
IWDG MODE
STOP [1:0] IOEN
rw rw rw rw
Debug support (DBG)
20 19 18
DBG_ DBG_ DBG_
TIM8_ TIM7_ TIM6_
STOP STOP STOP
rw rw rw
5 4 3 2
DBG_
_ Reserved STAND
BY
Res. rw
17 16
DBG_I2
DBG_
C2_SM
TIM5_
BUS_TI
STOP
MEOUT
rw rw
1 0
DBG_ DBG_
STOP SLEEP
rw rw
671/690