Spi Communication Using Dma (Direct Memory Addressing) - ST STM32F102 Series Reference Manual

RM0008
Note: This SPI offers two kinds of CRC calculation standard which depend directly on the data
frame format selected for the transmission and/or reception: 8-bit data (CR8) and 16-bit data
(CRC16-CCITT).
CRC calculation is enabled by setting the CRCEN bit in the SPI_CR1 register. This action
resets the CRC registers (SPI_RXCRCR and SPI_TXCRCR). When the CRCNEXT bit in
SPI_CR1 is set, the SPI_TXCRCR value is transmitted at the end of the current byte
transmission.
The CRCERR flag in the SPI_SR register is set if the value received in the shift register
during the SPI_TXCRCR value transmission does not match the SPI_RXCRCR value.
If data are present in the TX buffer, the CRC value is transmitted only after the transmission
of the data byte. During CRC transmission, the CRC calculator is switched off and the
register value remains unchanged.
Note: Please refer to the product specifications for availability of this feature.
SPI communication using CRC is possible through the following procedure:
● Program the CPOL, CPHA, LSBFirst, BR, SSM, SSI and MSTR values
●
Program the polynomial in the SPI_CRCPR register
● Enable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This
also clears the SPI_RXCRCR and SPI_TXCRCR registers
●
Enable the SPI by setting the SPE bit in the SPI_CR1 register
●
Start the communication and sustain the communication until all but one byte or half-
word have been transmitted or received.
●
On writing the last byte or half-word to the TX buffer, set the CRCNext bit in the
SPI_CR1 register to indicate that after transmission of the last byte, the CRC should be
transmitted. CRC calculation is frozen during the CRC transmission.
●
After transmitting the last byte or half word, the SPI transmits the CRC. The CRCNEXT
bit is reset. The CRC is also received and compared against the SPI_RXCRCR value.
If the value does not match, the CRCERR flag in SPI_SR is set and an interrupt can be
generated when the ERRIE bit in the SPI_CR2 register is set.
Note: With high bit rate frequencies, the user must take care when transmitting CRC. As the
number of used CPU cycles has to be as low as possible in the CRC transfer phase, the
calling of software functions in the CRC transmission sequence is forbidden to avoid errors
in the last data and CRC reception.
For high bit rate frequencies, the DMA mode is advised to avoid degradation of SPI speed
performance due to CPU accesses impacting the SPI bandwidth.
22.3.7

SPI communication using DMA (direct memory addressing)

To operate at its maximum speed, the SPI needs to be fed with the data for transmission and
the data received on the Rx buffer should be read to avoid overrun. To facilitate the transfers,
the SPI is implemented with a DMA facility with a simple request/acknowledge protocol.
DMA access is requested when the enable bit in the SPI_CR2 register is enabled. There are
separate requests for the Tx buffer and the Rx buffer.
DMA capability with CRC
When SPI communication is enabled with the CRC communication and the DMA mode, the
transmission and reception of the CRC bytes at the end of communication are done
automatically.
Serial peripheral interface (SPI)
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