Spi Data Register (Spi_Dr) - ST STM32F102 Series Reference Manual

Serial peripheral interface (SPI)
Bit 2 CHSIDE: Channel side
0: Channel Left has to be transmitted or has been received
1: Channel Right has to be transmitted or has been received
Note: Not used for the SPI mode
No meaning in PCM mode
Bit 1 TXE: Transmit buffer Empty
0: Tx buffer not empty
1: Tx buffer empty
Bit 0 RXNE: Receive buffer Not Empty
0: Rx buffer empty
1: Rx buffer not empty
22.5.4

SPI data register (SPI_DR)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 DR[15:0]: Data Register
Data received or to be transmitted.
The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for reading
(Receive buffer). A write to the data register will write into the Tx buffer and a read from the data
register will return the value held in the Rx buffer.
Notes for the SPI mode:
Depending on the data frame format selection bit (DFF in SPI_CR1 register), the data sent or
received is either 8-bit or 16-bit. This selection has to be made before enabling the SPI to ensure
correct operation.
For an 8-bit data frame, the buffers are 8-bit and only the LSB of the register (SPI_DR[7:0]) is used
for transmission/reception. When in reception mode, the MSB of the register (SPI_DR[15:8]) is
forced to 0.
For a 16-bit data frame, the buffers are 16-bit and the entire register, SPI_DR[15:0] is used for
transmission/reception.
574/690
12 11 10 9
rw rw rw rw
8 7 6 5
DR[15:0]
rw rw rw rw
4 3 2 1
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RM0008
0
rw