ST STM32F102 Series Reference Manual page 409

RM0008
Attribute memory space timing registers 2..4 (FSMC_PATT2..4)
Address offset: 0xA000 0000 + 0x4C + 0x20 * (x – 1), x = 2..4
Reset value: 0xFCFC FCFC
Each FSMC_PATTx (x = 2..4) read/write register contains the timing information for PC Card
or NAND Flash memory bank x, used for access to the attribute memory space of the 16-bit
PC Card/CompactFlash, or to access the NAND Flash for last address write access if timing
must differ from the other accesses (for Ready/Busy management, refer to
NAND-Flash ready/busy
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ATTHIZx
r/w
Bits 31:24 ATTHIZx: Attribute memory x databus HiZ time.
Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the start of a
PC CARD/NAND Flash write access to attribute memory space on socket x. Only valid for write
transaction:
0000 0000: 0 HCLK cycle
1111 1111: 255 HCLK cycles (default value after reset)
Bits 23:16 ATTHOLDx: Attribute memory x hold time.
Defines the number of HCLK (+1) clock cycles to hold address (and data for write access) after the
command deassertion (NWE, NOE), for PC CARD/NAND Flash read or write access to attribute
memory space on socket x
0000 0000: 1 HCLK cycle
1111 1111: 256 HCLK cycles (default value after reset)
Bits 15:8 ATTWAITx: Attribute memory x wait time.
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for
PC CARD/NAND Flash read or write access to attribute memory space on socket x. The duration
for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the
programmed value of HCLK:
0000 0000: 1 HCLK cycle (+ wait cycle introduced by deassertion of NWAIT)
1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) (default
value after reset)
Bits 7:0 ATTSETx: Attribute memory x setup time.
Defines the number of HCLK (+1) clock cycles to set up address before the command assertion
(NWE, NOE), for PC CARD/NAND Flash read or write access to attribute memory space on socket
x:
0000 0000: 1 HCLK cycle
1111 1111: 256 HCLK cycles (default value after reset)
management).
ATTHOLDx
r/w
Flexible static memory controller (FSMC)
9 8 7
ATTWAITx
r/w
Section 18.6.4:
6 5 4 3 2 1 0
ATTSETx
r/w
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