Figure 203. Bit Timing - ST STM32F102 Series Reference Manual

RM0008
A valid edge is defined as the first transition in a bit time from dominant to recessive bus
level provided the controller itself does not send a recessive bit.
If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so
that the sample point is delayed.
Conversely, if a valid edge is detected in BS2 instead of SYNC_SEG, BS2 is shortened by
up to SJW so that the transmit point is moved earlier.
As a safeguard against programming errors, the configuration of the Bit Timing Register
(CAN_BTR) is only possible while the device is in Standby mode.
Note: For a detailed description of the CAN bit timing and resynchronization mechanism, please
refer to the ISO 11898 standard.

Figure 203. Bit timing

SYNC_SEG
BaudRate
NominalBitTime
with:
t
t
t
t
BRP[9:0], TS1[3:0] and TS2[2:0] are defined in the CAN_BTR Register.
BIT SEGMENT 1 (BS1)
1 x t
q
1
----------------------------------------------
=
NominalBitTime
×
= t +
1
q
= t x (TS1[3:0] + 1),
BS1 q
= t x (TS2[2:0] + 1),
BS2 q
= (BRP[9:0] + 1) x t
q PCLK
where t refers to the Time quantum
q
= time period of the APB clock,
PCLK
NOMINAL BIT TIME
t
BS1
SAMPLE POINT
t + t
BS1 BS2
Controller area network (bxCAN)
BIT SEGMENT 2 (BS2)
t
BS2
TRANSMIT POINT
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