Dma Registers; Dma Interrupt Status Register (Dma_Isr) - ST STM32F102 Series Reference Manual

DMA controller (DMA)
9.4

DMA registers

Refer to
Note: In the following registers, all bits relative to channel6 and channel7 are not relevant for
DMA2 since it has only 5 channels.
9.4.1

DMA interrupt status register (DMA_ISR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28
Reserved
15 14 13 12
TEIF4 HTIF4 TCIF4 GIF4
r r r
Bits 31:28 Reserved, always read as 0.
Bits 27, 23, TEIFx: Channel x Transfer Error flag (x = 1 ..7)
19, 15, 11,
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
7, 3
DMA_IFCR register.
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x
Bits 26, 22, HTIFx: Channel x Half Transfer flag (x = 1 ..7)
18, 14, 10,
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
6, 2
DMA_IFCR register.
0: No half transfer (HT) event on channel x
1: A half transfer (HT) event occurred on channel x
Bits 25, 21, TCIFx: Channel x Transfer Complete flag (x = 1 ..7)
17, 13, 9, 5,
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
1
DMA_IFCR register.
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
Bits 24, 20, GIFx: Channel x Global interrupt flag (x = 1 ..7)
16, 12, 8, 4,
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
0
DMA_IFCR register.
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x
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Section 1.1 on page 32
27 26 25
TEIF7 HTIF7 TCIF7
r r r
11 10 9
TEIF3 HTIF3 TCIF3
r r r r
for a list of abbreviations used in the register descriptions.
24 23 22
GIF7 TEIF6 HTIF6 TCIF6
r r r
8 7 6
GIF3 TEIF2 HTIF2 TCIF2
r r r
21 20 19 18
GIF6 TEIF5 HTIF5
r r r r
5 4 3 2
GIF2 TEIF1 HTIF1
r r r r
RM0008
17 16
TCIF5 GIF5
r r
1 0
TCIF1 GIF1
r r