Sdio Command Response Register (Sdio_Respcmd); Sdio Response 0; Table 131. Response Type And Sdio_Respx Registers - ST STM32F102 Series Reference Manual

SDIO interface (SDIO)
19.9.5

SDIO Command Response Register (SDIO_RESPCMD)

Address offset: 0x10
Reset value: 0x0000 0000
The SDIO_RESPCMD register contains the command index field of the last command
response received. If the command response transmission does not contain the command
index field (long or OCR response), the RESPCMD field is unknown, although it must
contain 111111b (the value of the reserved field from the response).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:6 Reserved, always read as 0.
Bits 5:0 RESPCMD: Response command index. Read-only bit field. Contains the command index of the last
command response received.
19.9.6 SDIO response 0..4 register (SDIO_RESPx)
Address offset: (0x14 + (4*x)); x = 0..4
Reset value: 0x0000 0000
The SDIO_RESP0/1/2/3/4 registers contain the status of a card, which is part of the receive
response.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:0 CARDSTATUSx: see
The Card Status size is 32 or 127 bits, depending on the response type.

Table 131. Response type and SDIO_RESPx registers

Register
SDIO_RESP1
SDIO_RESP2
SDIO_RESP3
SDIO_RESP4
The most significant bit of the card status is received first. The SDIO_RESP3 register LSB is
always 0b.
456/690
Reserved
r
CARDSTATUSx
r
Table 131.
Short response
Card Status[31:0]
Unused
Unused
Unused
9 8 7 6 5 4 3
RESPCMD
9 8 7 6 5 4 3
Long response
Card Status [127:96]
Card Status [95:64]
Card Status [63:32]
Card Status [31:1]0b
RM0008
2 1 0
r
2 1 0