Usart Synchronous Mode; Figure 245. Break Detection In Lin Mode Vs. Framing Error Detection - ST STM32F102 Series Reference Manual

RM0008

Figure 245. Break detection in LIN mode vs. Framing error detection

In these examples, we suppose that LBDL=1 (11-bit break length), M=0 (8-bit data)
Case 1: break occurring after an Idle
RX line
RXNE / FE
Case 1: break occurring while a data is being received
RX line
RXNE / FE
24.3.8

USART synchronous mode

The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to
1. In synchronous mode, the following bits must be kept cleared:
●
LINEN bit in the USART_CR2 register,
●
SCEN, HDSEL and IREN bits in the USART_CR3 register.
The USART allows the user to control a bidirectional synchronous serial communications in
master mode. The SCLK pin is the output of the USART transmitter clock. No clock pulses
are sent to the SCLK pin during start bit and stop bit. Depending on the state of the LBCL bit
in the USART_CR2 register clock pulses will or will not be generated during the last valid
data bit (address mark). The CPOL bit in the USART_CR2 register allows the user to select
the clock polarity, and the CPHA bit in the USART_CR2 register allows the user to select the
phase of the external clock (see
During idle, preamble and send break, the external SCLK clock is not activated.
In synchronous mode the USART transmitter works exactly like in asynchronous mode. But
as SCLK is synchronized with TX (according to CPOL and CPHA), the data on TX is
synchronous.
In this mode the USART receiver works in a different manner compared to the
asynchronous mode. If RE=1, the data is sampled on SCLK (rising or falling edge,
depending on CPOL and CPHA), without any oversampling. A setup and a hold time must
be respected (which depends on the baud rate: 1/16 bit time).
Note: 1 The SCLK pin works in conjunction with the TX pin. Thus, the clock is provided only if the
transmitter is enabled (TE=1) and a data is being transmitted (the data register USART_DR
Universal synchronous asynchronous receiver transmitter (USART)
data 1 IDLE
LBD
data 1 data 2
1 data time
LBD
BREAK
1 data time
BREAK
Figure 246, Figure 247
data2 (0x55)
1 data time
data2 (0x55)
1 data time
& Figure 248).
data 3 (header)
data 3 (header)
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