Independent Trigger With Same Lfsr Generation; Independent Trigger With Different Lfsr Generation; Independent Trigger With Same Triangle Generation - ST STM32F102 Series Reference Manual

Digital-to-analog converter (DAC)
11.4.2

Independent trigger with same LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:
●
Set the two DAC channel trigger enable bits TEN1 and TEN2
●
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
●
Configure the two DAC channel WAVEx[1:0] bits as "01" and the same LFSR mask
value in the MAMPx[3:0] bits
●
Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD
or DHR8RD)
When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to
the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles
later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles
later). Then the LFSR2 counter is updated.
11.4.3

Independent trigger with different LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:
●
Set the two DAC channel trigger enable bits TEN1 and TEN2
●
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
●
Configure the two DAC channel WAVEx[1:0] bits as "01" and set different LFSR masks
values in the MAMP1[3:0] and MAMP2[3:0] bits
● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by
MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1
(three APB1 clock cycles later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by
MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the LFSR2 counter is updated.
11.4.4

Independent trigger with same triangle generation

To configure the DAC in this conversion mode, the following sequence is required:
●
Set the two DAC channel trigger enable bits TEN1 and TEN2
●
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
●
Configure the two DAC channel WAVEx[1:0] bits as "1x" and the same maximum
amplitude value in the MAMPx[3:0] bits
●
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same
triangle amplitude, is added to the DHR1 register and the sum is transferred into
192/690
RM0008