Clock Generator; Figure 228. Audio Sampling Frequency Definition - ST STM32F102 Series Reference Manual

Serial peripheral interface (SPI)
22.4.3

Clock generator

2
The I S bitrate determines the dataflow on the I
frequency.
2
I S bitrate = number of bits per channel × number of channels × sampling audio frequency
For a 16-bit audio, left and right channel, the I
2
I S bitrate = 16 × 2 × F
It will be: I

Figure 228. Audio sampling frequency definition

When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
Figure 229. I
I2SxCLK
1. Where x could be 2 or 3.
Figure 228
System Clock (provided by the HSI, the HSE or the PLL and sourcing the AHB clock).
The audio sampling frequency may be 48 kHz, 44.1 kHz, 22.05 kHz, 16 kHz or 8 kHz. In
order to reach the desired frequency, the linear divider needs to be programmed according
to the formulas below:
When the master clock is generated (MCKOE in the SPI_I2SPR register is set):
F = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
S
F = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
S
564/690
S
2
S bitrate = 32 x 2 x F
16-bit or 32-bit Left channel
sampling point
F : Audio sampling frequency
S
2
S clock generator architecture
8-bit Linear
Divider +
reshaping stage
MCKOE ODD I2SDIV[7:0]
presents the communication clock architecture. The I2SxCLK source is the
2
S data line and the I
2
S bitrate is calculated as follows:
if the packet length is 32-bit wide.
S
16-bit or 32-bit Right channel
32-bits or 64-bits
F
S
Divider by 4
I2SMOD
2
S clock signal
sampling point
0
Div2 0
1
1
MCKOE
CHLEN
RM0008
MCK
CK