Figure 209. Data Clock Timing Diagram - ST STM32F102 Series Reference Manual

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Figure 209. Data clock timing diagram

(from master)

(from slave)

Capture strobe

(from master)

(from slave)

Capture strobe

Note: These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register.

1. These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register.

Data frame format

Data can be shifted out either MSB-first or LSB-first depending on the value of the

LSBFIRST bit in the SPI_CR1 Register.

Each data frame is 8 or 16 bits long depending on the size of the data programmed using

the DFF bit in the SPI_CR1 register. The selected data frame format is applicable for

transmission and/or reception.

8 or 16 bits depending on Data Frame Format (see SPI_CR1)

8 or 16 bits depending on Data Frame Format (see SPI_CR1)

Serial peripheral interface (SPI)

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