Mailbox Registers - ST STM32F102 Series Reference Manual

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Controller area network (bxCAN)

Bits 25:24 SJW[1:0]: Resynchronization Jump Width

These bits define the maximum number of time quanta the CAN hardware is allowed to lengthen or

shorten a bit to perform the resynchronization.

Reserved, forced by hardware to 0.

Bits 22:20 TS2[2:0]: Time Segment 2

These bits define the number of time quanta in Time Segment 2.

Bits 19:16 TS1[3:0]: Time Segment 1

These bits define the number of time quanta in Time Segment 1

For more information on bit timing, please refer to

Reserved, forced by hardware to 0.

Bits 9:0 BRP[9:0]: Baud Rate Prescaler

These bits define the length of a time quanta.

= (BRP[9:0]+1) x t

Mailbox registers

This chapter describes the registers of the transmit and receive mailboxes. Refer to

Section 21.4.5: Message storage on page 512

Transmit and receive mailboxes have the same registers except:

The FMI field in the CAN_RDTxR register.

A receive mailbox is always write protected.

A transmit mailbox is write-enabled only while empty, corresponding TME bit in the

CAN_TSR register set.

There are 3 TX Mailboxes and 2 RX Mailboxes. Each RX Mailbox allows access to a 3 level

depth FIFO, the access being offered only to the oldest received message in the FIFO.

Each mailbox consist of 4 registers.

x (SJW[1:0] + 1)

x (TS2[2:0] + 1)

x (TS1[3:0] + 1)

Section 21.4.7: Bit timing on page

for detailed register mapping.

Three Tx Mailboxes

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