Figure 56. Counter Timing Diagram, Internal Clock Divided By 1; Figure 57. Counter Timing Diagram, Internal Clock Divided By 2; Figure 58. Counter Timing Diagram, Internal Clock Divided By 4 - ST STM32F102 Series Reference Manual

Advanced-control timers (TIM1&TIM8)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 56. Counter timing diagram, internal clock divided by 1

Figure 57. Counter timing diagram, internal clock divided by 2

Figure 58. Counter timing diagram, internal clock divided by 4

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CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow (cnt_udf)
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
05 04 03 02 01 00 36 35 34 33 32 31 30 2F
0002
0001 0000 0036 0035 0034 0033
0001
0000
RM0008
0036 0035