Power Control/Status Register (Pwr_Csr) - ST STM32F102 Series Reference Manual

RM0008
4.4.2

Power control/status register (PWR_CSR)

Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31 30 29
15 14 13
Reserved
Res.
Bits 31:9 Reserved, always read as 0.
Bit 8 EWUP: Enable WKUP pin
This bit is set and cleared by software.
0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup the
device from Standby mode.
1: WKUP pin is used for wakeup from Standby mode and forced in input pull down configuration
(rising edge on WKUP pin wakes-up the system from Standby mode).
Note: This bit is reset by a system Reset.
Bits 7:3 Reserved, always read as 0.
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: V /V
DD
1: V /V
DD
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after Standby or
reset until the PVDE bit is set.
Bit 1 SBF: Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset) or by
setting the CSBF bit in the
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUF: Wakeup Flag
This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset) or
by setting the CWUF bit in the
0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm
Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit)
when the WKUP pin level is already high.
28 27 26 25
12 11 10 9
is higher than the PVD threshold selected with the PLS[2:0] bits.
DDA
is lower than the PVD threshold selected with the PLS[2:0] bits.
DDA
Power control register (PWR_CR)
Power control register (PWR_CR)
24 23 22 21
Reserved
Res.
8 7 6
EWUP Reserved
rw Res.
Power control (PWR)
20 19 18
5 4 3 2
PVDO
r
17 16
1 0
SBF WUF
r r
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