Port Configuration Lock Register (Gpiox_Lckr) (X=A..g - ST STM32F102 Series Reference Manual

RM0008
7.2.7

Port configuration lock register (GPIOx_LCKR) (x=A..G)

This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit it is no longer possible to modify the value of
the port bit until the next reset.
Each lock bit freezes the corresponding 4 bits of the control register (CRL, CRH).
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
15 14 13
LCK15 LCK14 LCK13 LCK12
rw rw rw
Bits 31:17 Reserved
Bit 16 LCKK[16]: Lock key
This bit can be read anytime. It can only be modified using the Lock Key Writing Sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. GPIOx_LCKR register is locked until an MCU reset occurs.
LOCK Key Writing Sequence:
Write 1
Write 0
Write 1
Read 0
Read 1 (this read is optional but confirms that the lock is active)
Note: During the LOCK Key Writing sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence will abort the lock.
Bits 15:0 LCKy: Port x Lock bit y (y= 0 .. 15)
These bits are read write but can only be written when the LCKK bit is 0.
0: Port configuration not locked
1: Port configuration locked.
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
28 27 26 25
12 11 10 9
LCK11 LCK10 LCK9
rw rw rw rw
24 23 22
Reserved
Res.
8 7 6
LCK8 LCK7 LCK6
rw rw rw
21 20 19 18
5 4 3 2
LCK5 LCK4 LCK3 LCK2
rw rw rw rw
17 16
LCKK
rw
1 0
LCK1 LCK0
rw rw
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