Figure 210. I 2 S Block Diagram - ST STM32F102 Series Reference Manual

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Serial peripheral interface (SPI)

Figure 210. I

The SPI could function as an audio I

setting the I2SMOD bit in the SPI_I2SCFGR register). This interface uses almost the same

pins, flags and interrupts as the SPI.

S shares three common pins with the SPI:

SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time-

multiplexed data channels (in simplex mode only).

WS: Word Select (mapped on the NSS pin) is the data control signal output in master

mode and input in slave mode.

CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode

and serial clock input in slave mode.

S block diagram

Master control logic

baud rate generator

Address and data bus

BSY OVR MODF CRC

Shift register

First SPE BR2 BR1 BR0

S clock generator

S interface when the I

Communication

MSTR CPOL CPHA

S capability is enabled (by

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