Flexible static memory controller (FSMC)
16-bit NAND Flash
Table 97.
FSMC signal name
A[17]
A[16]
D[15:0]
NOE(= NRE)
NWE
NWAIT
There is no theoretical capacity limitation as the FSMC can manage as many address
cycles as needed.
Table 98.
FSMC signal name
A[10:0]
NIOS16
NIORD
NIOWR
NREG
D[15:0]
NCE4_1
NCE4_2
NWAIT
18.6.2
NAND Flash / PC Card supported memories and transactions
Table 99
not allowed (or not supported) by the NAND Flash / PC Card controller appear in gray.
400/690
16-bit NAND Flash
I/O
O
O
I/O
O
O
I
16-bit PC Card
I/O
O
I
O
O
O
I/O
O
O
NOE
O
NWE
O
I
CD
I
below shows the supported devices, access modes and transactions. Transactions
NAND Flash address latch enable (ALE) signal
NAND Flash command latch enable (CLE) signal
16-bit multiplexed, bidirectional address/data bus
Output enable (memory signal name: read enable, NRE)
Write enable
NAND Flash ready/busy input signal to the FSMC
Address bus
Data transfer width in I/O space (16-bit or 8-bit transfer)
Output enable for I/O space
Write enable for I/O space
Register signal indicating if access is in Common or Attribute
space
Bidirectional databus
Chip select 1
Chip select 2 (indicates if access is 16-bit or 8-bit)
Output enable
Write enable
PC Card wait input signal to the FSMC
PC Card presence detection
Function
Function
RM0008
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