Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr) - ST STM32F102 Series Reference Manual

Reset and clock control (RCC)
Bit 4 IOPCEN I/O port C clock enable
Set and reset by software.
0: I/O port C clock disabled
1:I/O port C clock enabled
Bit 3 IOPBEN I/O port B clock enable
Set and reset by software.
0: I/O port B clock disabled
1:I/O port B clock enabled
Bit 2 IOPAEN I/O port A clock enable
Set and reset by software.
0: I/O port A clock disabled
1:I/O port A clock enabled
Bit 1 Reserved, always read as 0.
Bit 0 AFIOEN Alternate function I/O clock enable
Set and reset by software.
0: Alternate Function I/O clock disabled
1:Alternate Function I/O clock enabled
6.3.8

APB1 peripheral clock enable register (RCC_APB1ENR)

Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
31 30 29 28
DAC PWR
Reserved
EN EN
Res. rw rw
15 14 13 12
SPI3 SPI2
Reserved
EN EN
rw rw Res.
Bits 31:30 Reserved, always read as 0.
Bit 29 DACEN DAC interface clock enable
Set and reset by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN Power interface clock enable
Set and reset by software.
0: Power interface clock disabled
1: Power interface clock enable
90/690
27 26 25 24
BKP CAN
Res. Res.
EN EN
rw Res. rw Res.
11 10 9 8
WWD
Reserved
GEN
rw Res.
23 22 21 20
USB I2C2 I2C1 UART5E
EN EN EN N
rw rw rw rw
7 6 5 4
TIM7 TIM6
EN EN
rw rw
RM0008
19 18 17
UART4 USART USART
EN 3EN 2EN
rw rw rw
3 2 1
TIM5 TIM4 TIM3
EN EN EN
rw rw rw
16
Res.
Res.
0
TIM2
EN
rw