Pinout And Debug Port Pins; Swj Debug Port Pins; Flexible Swj-Dp Pin Assignment; Table 158. Swj Debug Port Pins - ST STM32F102 Series Reference Manual

Debug support (DBG)
JTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only
the SWCLK and SWDIO pins.
This sequence is:
1. Send more than 50 TCK cycles with TMS (SWDIO) =1
2. Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted
first)
3. Send more than 50 TCK cycles with TMS (SWDIO) =1
26.4

Pinout and debug port pins

The STM32F10xxx MCU is available in various packages with different numbers of available
pins. As a result, some functionality related to pin availability may differ between packages.
26.4.1

SWJ debug port pins

Five pins are used as outputs from the STM32F10xxx for the SWJ-DP as alternate functions
of General Purpose I/Os. These pins are available on all packages.

Table 158. SWJ debug port pins

SWJ-DP pin name
JTMS/SWDIO
JTCK/SWCLK
JTDI
JTDO/TRACESWO
JNTRST
26.4.2

Flexible SWJ-DP pin assignment

After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned
as dedicated pins immediately usable by the debugger host (note that the trace outputs are
not assigned except if explicitly programmed by the debugger host).
However, the STM32F10xxx MCU implements the REMAP_DBGAFR register to disable
some part or all of the SWJ-DP port and so releases the associated pins for General
Purpose I/Os usage. This register is mapped on an APB bridge connected to the Cortex-M3
System Bus. Programming of this register is done by the user software program and not the
debugger host.
656/690
JTAG debug port
Type Description
JTAG Test Mode
I
Selection
I JTAG Test Clock
I JTAG Test Data Input
O JTAG Test Data Output
I JTAG Test nReset
SW debug port
Type Debug assignment
Serial Wire Data
I/O
Input/Output
I Serial Wire Clock
- -
TRACESWO if async trace
-
is enabled
- -
RM0008
Pin
assign
ment
PA13
PA14
PA15
PB3
PB4