Control Register 2 (Timx_Cr2) - ST STM32F102 Series Reference Manual

RM0008
Bit 2 URS: Update Request Source.
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled. These
events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bit 1 UDIS: Update DIsable.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC,
CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware
reset is received from the slave mode controller.
Bit 0 CEN: Counter enable.
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit automatically by hardware.
CEN is cleared automatically in one pulse mode, when an update event occurs.
13.4.2

Control register 2 (TIMx_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13
Bits 15:8 Reserved, always read as 0.
Bit 7 TI1S: TI1 Selection.
0: The TIMx_CH1 pin is connected to TI1 input.
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
See also
12 11 10 9
Reserved
Section 12.3.18: Interfacing with Hall sensors on page 241
8 7 6 5
TI1S MMS[2:0]
rw rw rw
General-purpose timer (TIMx)
4 3 2 1
CCDS
Reserved
rw rw
0
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