Synchronous Burst Read; Table 89. Fsmc_Bcrx Bit Fields; Table 90. Fsmc_Tcrx Bit Fields - ST STM32F102 Series Reference Manual

RM0008
Table 89.
Bit No.
31-15
14
13-10
9
8
7
6
5-4
3-2
1
0
Table 90.
Bit No.
31-30
29-20
19-16
15-8
7-4
3-0
18.5.5

Synchronous burst read

The memory clock, CLK, is a submultiple of HCLK according to the value of parameter
CLKDIV.
NOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet
this constraint, the FSMC does not issue the clock to the memory during the first internal
clock cycle of the synchronous access (before NADV assertion). This guarantees that the
rising edge of the memory clock occurs in the middle of the NADV low pulse.
FSMC_BCRx bit fields
Bit name
0x0000
EXTMOD 0x0
0x0
WAITPOL Meaningful only if bit 15 is 1.
BURSTEN 0x0
-
FACCEN Set according to memory support
MWID As needed
MTYP 10 (NOR)
MUXEN 0x1
MBKEN 0x1
FSMC_TCRx bit fields
Bit name
0
BUSTURN Duration of the last phase of the access (BUSTURN+1 HCLK)
Duration of the second access phase (DATAST+3 HCLK cycles for
DATAST read accesses and DATAST+1 HCLK cycles for write accesses).
This value cannot be 0 (minimum is 1)
Duration of the middle phase of the access (ADDHLD+1 HCLK
cycles).
ADDHLD
This value cannot be 0 (minimum is 1).
ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles).
Flexible static memory controller (FSMC)
Value to set
Value to set
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