Figure 258. Block Diagram Of Stm32F10Xxx-Level And Cortex-M3-Level Debug Support - ST STM32F102 Series Reference Manual

Debug support (DBG)

Figure 258. Block diagram of STM32F10xxx-level and Cortex-M3-level debug support

STM32F10x debug support
Cortex-M3 debug support
JTMS/
SWDIO
JTDI
JTDO/
SWJ-DP
TRACESWO
JNTRST
JTCK/
SWCLK
Note: The debug features embedded in the Cortex-M3 core are a subset of the ARM CoreSight
Design Kit.
The ARM Cortex-M3 core provides integrated on-chip debug support. It is comprised of:
●
SWJ-DP: Serial wire / JTAG debug port
●
AHP-AP: AHB access
●
ITM: Instrumentation trace macrocell
●
FPB: Flash patch breakpoint
●
DWT: Data watchpoint trigger
●
TPUI: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
It also includes debug features dedicated to STM32F10xxx:
●
Flexible debug pinout assignment
● MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the ARM Cortex-M3 core, refer
to the Cortex-M3 r1p1 Technical Reference Manual (TRM) and to the CoreSight Design Kit
r1p0 TRM.
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Bus Matrix
Data
Cortex-M3
Core
AHB-AP
Internal Private
Peripheral Bus (PPB)
ort
p
DCode
interface
System
interface
External Private
Peripheral Bus (PPB)
Bridge TPIU
NVIC
DWT
FPB
ITM
RM0008
TRACESWO
Trace Port
TRACECK
TRACED[3:0]
DBGMCU