Spi_I S Prescaler Register (Spi_I2Spr) - ST STM32F102 Series Reference Manual

Serial peripheral interface (SPI)
2
22.5.9 SPI_I S Prescaler register (SPI_I2SPR)
Address offset: 20h
Reset value: 0000 0010 (0002h)
15 14 13
Reserved
Res.
Bits 15:10 Reserved: Forced to 0 by hardware
Bit 9 MCKOE: Master Clock Output Enable
0: Master clock output is disabled
1: Master clock output is enabled
Notes: This bit should be configured when the I
master mode.
Not used in SPI mode.
Bit 8 ODD: Odd factor for the prescaler
0: real divider value is = I2SDIV *2
1: real divider value is = (I2SDIV * 2)+1
Refer to Section 22.4.3 on page 564
Notes: This bit should be configured when the I
master mode.
Not used in SPI mode
Bit 7:0 I2SDIV: I
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
Refer to
Notes: These bits should be configured when the I
master mode.
Not used in SPI mode.
578/690
12 11 10 9
MCKO
E
rw
2
S Linear prescaler
Section 22.4.3 on page 564
8 7 6 5
ODD
rw
2
S is disabled. It is used only when the I
2
S is disabled. It is used only when the I
2
S is disabled. It is used only when the I
RM0008
4 3 2 1
I2SDIV
rw
2
S is in
2
S is in
2
S is in
0