ST STM32F102 Series Reference Manual page 329

RM0008
Table 60. TIMx register map and reset values (continued)
Offset Register
TIMx_CCMR2
Output Compare
mode
Reset value
0x1C
TIMx_CCMR2
Input Capture
mode
Reset value
TIMx_CCER
0x20
Reset value
TIMx_CNT
0x24
Reset value
TIMx_PSC
0x28
Reset value
TIMx_ARR
0x2C
Reset value
0x30
TIMx_CCR1
0x34
Reset value
TIMx_CCR2
0x38
Reset value
TIMx_CCR3
0x3C
Reset value
TIMx_CCR4
0x40
Reset value
0x44
TIMx_DCR
0x48
Reset value
TIMx_DMAR
0x4C
Reset value
Refer to
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 1 on page 36 for the register boundary addresses.
General-purpose timer (TIMx)
OC4M
[2:0]
0 0 0 0
IC4F[3:0]
0 0 0 0
0 0
0 0 0 0
0 0 0 0
0 0 0 0
Reserved
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
Reserved
0
0 0 0 0
CC4S OC3M
[1:0] [2:0]
0 0 0 0 0 0 0 0 0
IC4
CC4S
PSC IC3F[3:0] PSC
[1:0]
[1:0]
0 0 0 0 0 0 0 0 0
0 0 0 0
CNT[15:0]
0 0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0 0
ARR[15:0]
0 0 0 0 0 0 0 0 0
CCR1[15:0]
0 0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0 0
DBL[4:0] DBA[4:0]
Reserved
0 0 0 0 0 0
DMAB[15:0]
0 0 0 0 0 0 0 0 0
CC3S
[1:0]
0 0 0
IC3
CC3S
[1:0]
[1:0]
0 0 0
0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
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