I 2 S Interrupts; Dma Features; Spi And I S Registers; Spi Control Register 1 (Spi_Cr1) - ST STM32F102 Series Reference Manual

RM0008
Overrun flag (OVR)
This flag is set when data are received and the previous data have not yet been read from
SPI_DR. As a result, the incoming data are lost. An interrupt may be generated if the ERRIE
bit is set in SPI_CR2.
In this case, the receive buffer contents are not updated with the newly received data from
the transmitter device. A read operation to the SPI_DR register returns the previous
correctly received data. All other subsequently transmitted half-words are lost.
Clearing the OVR bit is done by a read operation on the SPI_DR register followed by a read
access to the SPI_SR register.
2
22.4.8 I S interrupts
Table 147

Table 147. I

Transmit buffer empty flag
Receive buffer not empty flag
Overrun error
Underrun error
22.4.9

DMA features

DMA is working in exactly the same way as for the SPI mode. There is no difference on the
2
I S. Only the CRC feature is not available in I
protection system.
22.5 SPI and I
Refer to
22.5.1 SPI Control Register 1 (SPI_CR1) (not used in I
Address offset: 0x00
Reset value: 0x0000)
15 14 13
BIDI BIDI CRC CRC
MODE OE EN NEXT
rw rw rw
2
provides the list of I
2
S interrupt requests
Interrupt event
2
S registers
Section 1.1 on page 32
12 11 10 9
RX
DFF SSM
ONLY
rw rw rw rw
S interrupts.
Event flag
TXE
RXNE
OVR
UDR
2
S mode since there is no data transfer
for a list of abbreviations used in register descriptions.
8 7 6
LSB
SSI SPE
FIRST
rw rw rw
Serial peripheral interface (SPI)
Enable Control bit
TXEIE
RXNEIE
ERRIE
2
S mode)
5 4 3 2
BR [2:0] MSTR
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1 0
CPOL CPHA
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