Figure 80. Center-Aligned Pwm Waveforms (Arr=8); Figure 109. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6 - ST STM32F102 Series Reference Manual

RM0008
Table 174. Document revision history (continued)
Date
19-Oct-2007
continued
Revision
Figure 109: Counter timing diagram, internal clock divided by 1,
TIMx_ARR=0x6
modified.
CKD definition modified in
Bit 8 and Bit 9 added to
(BKP_RTCCR).
Bit 15 and Bit 16 added to
debug mode on page 596
Stop and Standby modified in
Table 9: Sleep-on-exit
HSITRIM[4:0] bit description modified in
(RCC_CR). Note modified in MCO description in
configuration register
register map and reset values on page
Bits 15:0 description modified in
(GPIOx_BRR)
Figure 10, Figure
Section 2.3.4: Embedded Flash memory on page 39
REV_ID bit description added to
Reset value modified in
HSITRIM[4:0] description modified.
Section 7.1.1 on page 99
GPIO registers on page
Table 10: Stop
1
Clock control register (RCC_CR)
continued
Note added in ASOS and ASOE bit descriptions in
Section 26.15.2: Debug support for timers, watchdog, bxCAN and I2C
modified. Table 173: DBG - register map and reset values
Section 20.5.3: Buffer descriptor table
Center-aligned mode (up/down counting) on page 215
mode (up/down counting) on page 282
Figure 80: Center-aligned PWM waveforms (ARR=8) on page 230
Figure 126: Center-aligned PWM waveforms (ARR=8) on page 295
modified.
RSTCAL description modified in
(ADC_CR2).
Note changed below
clock). Note added below
ADC conversion time modified in
Auto-injection on page 154
Note added in
interleaved. Note added to
GPIO ports PD0/PD1. Small text changes. Internal LSI RC frequency
changed from 32 to 40 kHz.
input clock) updated. Option byte addresses corrected in
map and Table 3: Flash module organization (medium-density
Information block organization modified in
memory.
External event that trigger ADC conversion is EXTI line instead of external
interrupt (see
Appendix A: Important notes on page 500
Changes
and Figure 124: Output compare mode, toggle on OC1.
Section 13.4.1: Control register 1
Section 5.4.2: RTC clock calibration register
DBGMCU_CR on page
added.
Table 7: Low-power mode
modified. Debug mode on page 56
(RCC_CFGR). RCC_CR row modified in
Section 7.2.6: Port bit reset register
(x=A..G). Embedded boot loader on page 43
12, Figure 13, Figure 14
DBGMCU_IDCODE on page
Clock control register (RCC_CR) on page 77
modified. Bit definitions modified in
105. Wakeup latency description modified in
mode.
reset value modified.
Section 10.12.3: ADC control register 2
Table 63: Watchdog timeout period (with 40 kHz input
Figure 8: Clock
Section 10.2: ADC main
updated.
Section 10.9.9: Combined injected simultaneous +
Section 7.3.2: Using OSC_IN/OSC_OUT pins as
Table 63: Watchdog timeout period (with 40 kHz
Section 10: Analog-to-digital converter
Revision history
(TIMx_CR1).
671. Section 23.5: I
summary.
modified.
Section 6.3.1: Clock control register
Section 6.3.2: Clock
96.
added.
and Figure 15 modified.
modified.
Section 7.2:
5.4.2 on page
updated.
clarified.
and Center-aligned
updated.
tree.
features.
Figure 2: Memory
Section 2.3.4: Embedded Flash
(ADC)).
added.
2
C
RCC -
659.
and
63.
and
devices).
681/690