Adc Control Register 2 (Adc_Cr2) - ST STM32F102 Series Reference Manual

Analog-to-digital converter (ADC)
Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits
These bits are set and cleared by software. They select the input channel to be guarded by the
Analog Watchdog.
00000: ADC analog input Channel0
00001: ADC analog input Channel1
....
01111: ADC analog input Channel15
10000: ADC analog input Channel16
10001: ADC analog input Channel17
Other values reserved.
Note: ADC1 analog inputs Channel16 and Channel17 are internally connected to the temperature
sensor and to V
ADC2 analog inputs Channel16 and Channel17 are internally connected to V
ADC3 analog inputs Channel9, Channel14, Channel15, Channel16 and Channel17 are
connected to V
10.12.3

ADC control register 2 (ADC_CR2)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
JEXTT
JEXTSEL[2:0]
RIG
rw rw rw
Bits 31:24 Reserved, must be kept cleared.
Bit 23 TSVREFE: Temperature Sensor and V
This bit is set and cleared by software to enable/disable the temperature sensor and V
channel. In devices with dual ADCs this bit is present only in ADC1.
0: Temperature sensor and V
1: Temperature sensor and V
Bit 22 SWSTART: Start Conversion of regular channels
This bit is set by software to start conversion and cleared by hardware as soon as conversion starts.
It starts a conversion of a group of regular channels if SWSTART is selected as trigger event by the
EXTSEL[2:0] bits.
0: Reset state
1: Starts conversion of regular channels
Bit 21 JSWSTART: Start Conversion of injected channels
This bit is set by software and cleared by software or by hardware as soon as the conversion starts.
It starts a conversion of a group of injected channels (if JSWSTART is selected as trigger event by
the JEXTSEL[2:0] bits.
0: Reset state
1: Starts conversion of injected channels
172/690
, respectively.
REFINT
.
SS
27 26 25
Reserved
Res.
11 10 9
ALIGN Reserved
rw rw Res.
REFINT
REFINT
24 23 22 21
TSVRE SWST JSWST
FE ART ART
rw rw rw
8 7 6
DMA Reserved
rw Res.
Enable
REFINT
channel disabled
channel enabled
SS
20 19 18
EXTT
EXTSEL[2:0]
RIG
rw rw rw
5 4 3 2
RST
CAL
CAL
rw rw
RM0008
.
17 16
Res.
rw
1 0
CONT ADON
rw rw
REFINT