ST STM32F102 Series Reference Manual page 89

RM0008
Bits 31:16 Reserved, always read as 0.
Bit 15 ADC3EN ADC 3 interface clock enable
Set and reset by software.
0: ADC 3 interface clock disabled
1: ADC 3 interface clock enabled
Bit 14 USART1EN USART1 clock enable
Set and reset by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 TIM8EN TIM8 Timer clock enable
Set and reset by software.
0: TIM8 timer clock disabled
1: TIM8 timer clock enabled
Bit 12 SPI1EN SPI 1 clock enable
Set and reset by software.
0: SPI 1 clock disabled
1: SPI 1 clock enabled
Bit 11 TIM1EN TIM1 Timer clock enable
Set and reset by software.
0: TIM1 timer clock disabled
1: TIM1 timer clock enabled
Bit 10 ADC2EN ADC 2 interface clock enable
Set and reset by software.
0: ADC 2 interface clock disabled
1: ADC 2 interface clock enabled
Bit 9 ADC1EN ADC 1 interface clock enable
Set and reset by software.
0: ADC 1 interface disabled
1: ADC 1 interface clock enabled
Bit 8 IOPGEN I/O port G clock enable
Set and reset by software.
0: I/O port G clock disabled
1: I/O port G clock enabled
Bit 7 IOPFEN I/O port F clock enable
Set and reset by software.
0: I/O port F clock disabled
1: I/O port F clock enabled
Bit 6 IOPEEN I/O port E clock enable
Set and reset by software.
0: I/O port E clock disabled
1: I/O port E clock enabled
Bit 5 IOPDEN I/O port D clock enable
Set and reset by software.
0: I/O port D clock disabled
1: I/O port D clock enabled
Reset and clock control (RCC)
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